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Core: Handle reserve instruction 31

This commit is contained in:
zilmar 2022-09-19 12:12:08 +09:30
parent a79a8a9276
commit 05d46c9487
7 changed files with 32 additions and 3 deletions
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8
Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp
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@ -141,7 +141,7 @@ R4300iOp::Func * R4300iOp::BuildInterpreter()
Jump_Opcode[28] = UnknownOpcode;
Jump_Opcode[29] = UnknownOpcode;
Jump_Opcode[30] = UnknownOpcode;
Jump_Opcode[31] = UnknownOpcode;
Jump_Opcode[31] = ReservedInstruction;
Jump_Opcode[32] = LB;
Jump_Opcode[33] = LH;
Jump_Opcode[34] = LWL;
@ -2697,6 +2697,12 @@ void R4300iOp::COP1_L_CVT_D()
}
// Other functions
void R4300iOp::ReservedInstruction()
{
g_Reg->DoIllegalInstructionException(g_System->m_PipelineStage == PIPELINE_STAGE_JUMP);
g_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
g_System->m_JumpToLocation = (*_PROGRAM_COUNTER);
}
void R4300iOp::UnknownOpcode()
{

1
Source/Project64-core/N64System/Interpreter/InterpreterOps.h
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@ -207,6 +207,7 @@ public:
static void COP1_L_CVT_D();
// Other functions
static void ReservedInstruction();
static void UnknownOpcode();
static Func* BuildInterpreter();

2
Source/Project64-core/N64System/Interpreter/InterpreterOps32.cpp
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@ -50,7 +50,7 @@ R4300iOp32::Func * R4300iOp32::BuildInterpreter()
Jump_Opcode[28] = R4300iOp::UnknownOpcode;
Jump_Opcode[29] = R4300iOp::UnknownOpcode;
Jump_Opcode[30] = R4300iOp::UnknownOpcode;
Jump_Opcode[31] = R4300iOp::UnknownOpcode;
Jump_Opcode[31] = R4300iOp::ReservedInstruction;
Jump_Opcode[32] = LB;
Jump_Opcode[33] = LH;
Jump_Opcode[34] = LWL;

4
Source/Project64-core/N64System/Mips/R4300iInstruction.cpp
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@ -527,6 +527,10 @@ void R4300iInstruction::DecodeName(void)
strcpy(m_Name, "LDR");
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
break;
case R4300i_RESERVED31:
strcpy(m_Name, "Reserved(31)");
sprintf(m_Param, "");
break;
case R4300i_LB:
strcpy(m_Name, "LB");
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);

3
Source/Project64-core/N64System/Mips/R4300iOpcode.h
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@ -87,7 +87,8 @@ enum R4300iOpCodes
R4300i_DADDIU = 25,
R4300i_LDL = 26,
R4300i_LDR = 27,
R4300i_LB = 32,
R4300i_RESERVED31 = 31,
R4300i_LB = 32,
R4300i_LH = 33,
R4300i_LWL = 34,
R4300i_LW = 35,

16
Source/Project64-core/N64System/Mips/Register.cpp
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@ -546,6 +546,22 @@ bool CRegisters::DoIntrException(bool DelaySlot)
return true;
}
void CRegisters::DoIllegalInstructionException(bool DelaySlot)
{
CAUSE_REGISTER = EXC_II;
if (DelaySlot)
{
CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4;
}
else
{
EPC_REGISTER = m_PROGRAM_COUNTER;
}
m_PROGRAM_COUNTER = 0x80000180;
STATUS_REGISTER |= STATUS_EXL;
}
void CRegisters::DoOverflowException(bool DelaySlot)
{
CAUSE_REGISTER = EXC_OV;

1
Source/Project64-core/N64System/Mips/Register.h
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@ -269,6 +269,7 @@ public:
void DoTrapException( bool DelaySlot );
void DoCopUnusableException( bool DelaySlot, int32_t Coprocessor );
bool DoIntrException( bool DelaySlot );
void DoIllegalInstructionException(bool DelaySlot);
void DoOverflowException(bool DelaySlot);
void DoTLBReadMiss(bool DelaySlot, uint32_t BadVaddr);
void DoTLBWriteMiss(bool DelaySlot, uint32_t BadVaddr);