zilmar
1864adcb35
Core: improve the accuracy of COP1_S_ADD
2023-02-21 14:54:22 +10:30
zilmar
f802b18cdc
Core: Change to using fenv.h instead of including the code directly
2023-01-30 10:07:51 +10:30
zilmar
0e52bfb185
Core: Fix the allocation of rdram size if set in the rdb
2023-01-23 08:30:13 +10:30
zilmar
210ebd42de
Core: have an option for rdram to be different between known and unknown roms
2023-01-16 20:53:48 +10:30
zilmar
531a7df959
Core: Improve StoreInstruc
2023-01-09 14:26:35 +10:30
zilmar
80aecdc5e3
Core: Improve R4300iOp::COP1_CT
2023-01-02 19:49:19 +10:30
zilmar
c0341bb759
Core: Code clean up for clang
2022-12-19 15:35:17 +10:30
zilmar
6c154f6547
Core: Add Cop2/Cop3 handling exception
2022-12-12 21:29:16 +10:30
zilmar
d3afe97d38
Core: Initialize FPR_Ctrl[Revision] to 0xA00
2022-12-12 15:27:07 +10:30
zilmar
d35d2e6abe
Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction
2022-12-05 12:23:09 +10:30
Squall Leonhart
8eecb0c823
Extend mempak Index Table to the intended 256 bytes, so that the default checksum is actually correct, and include the backup of that data. ( #2304 )
...
* just a test to see what happens
* duplicate the full 256 bytes.
* Didn't need to duplicate it after all.
The index table wasn't actually 256 bytes as intended, so the checksum was invalid.
Cruis'n'USA 1.0 didn't like this one bit.
* fully duplicate it after all just in case of a rare case
where a game breaks without the backup of the checksum and table.
* this looks properly duplicated now.
perhaps
2022-11-24 07:49:48 +10:30
zilmar
989827cb77
Core: Do not set m_MemoryReadMap/m_MemoryWriteMap if tlb mapping is outside rdram
2022-11-14 21:20:28 +10:30
zilmar
97e3f50007
Core: Update mask of registers in CRegisters::Cop0_MT
2022-11-14 20:56:21 +10:30
zilmar
cabcd2cc95
Core: Handle masking of random in CSystemTimer::UpdateTimers
2022-11-14 11:19:02 +10:30
zilmar
48da86bea1
Core: if Rom is larger than ISViewerHandler, then use rom handler
2022-11-08 10:54:01 +10:30
zilmar
b3c6858b69
Core: Change COP0 registers to use an enum
2022-11-07 09:24:58 +10:30
zilmar
4525e8b6f3
Core: Move IMEM/DMEM into SPRegistersHandler
2022-10-17 17:29:05 +10:30
zilmar
96244cd6fd
Core: Update NonMemory Access to pifram
2022-10-17 11:31:54 +10:30
zilmar
53e00b8023
Core: Clean up masking of COP0 registers
2022-10-17 09:06:22 +10:30
zilmar
9186dcab39
Core: Allow reading from ISViewerHandler
2022-10-17 08:59:26 +10:30
zilmar
c16307ec0f
Core: Move Pifram code into PifRamHandler
2022-10-17 08:27:52 +10:30
zilmar
761a1ee52a
Code clean up
2022-10-10 10:52:17 +10:30
zilmar
0d7f25138c
Core: Do not check sign extension in 32bit core
2022-10-04 09:47:45 +10:30
zilmar
8391cdafde
Core: Fix masking of context
2022-10-03 21:48:09 +10:30
zilmar
da138bf38b
Project64: Exception when address not sign extended
2022-10-03 18:35:50 +10:30
zilmar
82d9027374
Core: Fix up XContext
2022-10-03 11:29:21 +10:30
zilmar
42cc34964b
Core: Sign extend cop0
2022-10-03 09:34:13 +10:30
zilmar
a2981ff4d8
Core: Make Load/Store use 64bit vaddr
2022-09-19 21:36:36 +09:30
zilmar
1c77f6f0fd
Core: Make Cop0 64bit
2022-09-19 16:36:44 +09:30
zilmar
21b193152a
Core: Fix CMipsMemoryVM::MemoryValue64 for sdl/sdr
2022-09-19 12:13:19 +09:30
zilmar
05d46c9487
Core: Handle reserve instruction 31
2022-09-19 12:12:08 +09:30
zilmar
a640ecfbc0
Core: CMipsMemoryVM::SB_NonMemory should return false just on exception
2022-09-05 21:20:07 +09:30
zilmar
e171adfef6
Core: Clean up formatting of register names
2022-09-05 16:47:51 +09:30
zilmar
29526583a6
Core: Give cop0 registers names
2022-09-05 16:38:30 +09:30
zilmar
18b9892bc7
Core: Add handling of overflow exception
2022-09-05 16:35:13 +09:30
zilmar
0371c20d32
Core: Use BreakOnUnhandledMemory in SPRegistersHandler when breaking
2022-09-05 11:00:15 +09:30
zilmar
4218cbad23
Core: R4300iInstruction::DecodeSpecialName - Fix up SLL param
2022-08-29 08:27:47 +09:30
zilmar
9b16d29792
Core: Add rom write decay and some code clean up
2022-08-22 12:47:44 +09:30
zilmar
51c9867e76
Core: Get the recompiler to be use globals less
2022-08-08 20:22:51 +09:30
zilmar
5ea06d958e
Core: have SB/SH be able to write to rom handler
2022-08-08 19:33:16 +09:30
zilmar
18870634a5
Core: Clean up some 64bit warnings
2022-08-01 13:15:52 +09:30
zilmar
10d23486c6
Core: Add option to break on address exception
2022-08-01 10:38:12 +09:30
zilmar
cffeceef70
Core: Handle rom written to better
2022-08-01 10:15:56 +09:30
zilmar
d37d0dc7a5
Core: Dissasm of DMFC0 was showing the wrong reg
2022-08-01 10:02:07 +09:30
zilmar
7b851e6b6e
Core: Break on unhandled memory
2022-08-01 10:00:07 +09:30
zilmar
63051df71e
Core: Another fix at 64dd
2022-07-25 22:00:41 +09:30
zilmar
09b535551d
Core: Move DelaySlotEffectsCompare into R4300iInstruction
2022-07-25 16:35:42 +09:30
zilmar
0abc7ccaa4
Core: Move OpHasDelaySlot into R4300iInstruction
2022-07-25 14:23:12 +09:30
zilmar
15466b6a9b
Core: Fix unaligned rom access with LH/LB
2022-07-25 14:08:09 +09:30
zilmar
1a8a4dd50f
Core: Fix some bugs added to R4300iInstruction Param
2022-07-25 11:57:19 +09:30