zilmar
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b74e21d056
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Android: Show base dir to splash logs when starting
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2023-10-26 11:17:49 +10:30 |
zilmar
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bf480623bd
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[Android] Add Android/Bridge to clang checking
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2023-10-26 11:05:20 +10:30 |
zilmar
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8f062975c3
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Core: improve DisplayControlRegHandler::Write32
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2023-10-19 19:28:38 +10:30 |
zilmar
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d6a2ae80c1
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Core: Remove SystemRegisters
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2023-10-19 14:56:53 +10:30 |
zilmar
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d58168bcb9
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Core: R4300iOp access the registers directly, not through CSystemRegisters
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2023-10-19 12:52:33 +10:30 |
zilmar
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4d78f56aa2
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Core: In R4300iOp have a member variable for system, reg, mmu
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2023-10-19 12:31:26 +10:30 |
zilmar
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ae0097550f
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Core: Make R4300iOp opcodes not static
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2023-10-19 11:43:32 +10:30 |
zilmar
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7f42f70283
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Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
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2023-10-19 10:28:25 +10:30 |
zilmar
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d3edbf6dda
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Core: move CInterpreterCPU into R4300iOp
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2023-10-19 09:32:42 +10:30 |
zilmar
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d4dbc5a3f4
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Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
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2023-10-14 11:53:35 +10:30 |
zilmar
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00c5057b17
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Core: Make sure precision is correct for COP1_D_SQRT
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2023-10-13 00:16:14 +10:30 |
zilmar
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3a68d3d92a
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Core: LL/LLD store address
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2023-10-12 19:55:29 +10:30 |
zilmar
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a6405cfa2d
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Core: Add masking around DPC_START_REG/DPC_END_REG
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2023-10-12 17:50:58 +10:30 |
zilmar
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4e71221147
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Core: Fix up FPU mode register location
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2023-10-12 14:53:44 +10:30 |
zilmar
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befa57924d
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Core: Fix clang compile issues
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2023-10-05 15:01:09 +10:30 |
zilmar
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f73c3708a5
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Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
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2023-10-05 14:45:17 +10:30 |
zilmar
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e74e8f6a23
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Core: Have load/store ops be able to use 64bit addresses
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2023-10-05 14:28:32 +10:30 |
zilmar
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9f07fe2aac
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Core: Get tlb addresses to be 64bit
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2023-10-05 13:42:31 +10:30 |
zilmar
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4b844495b7
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Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
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2023-10-05 13:10:45 +10:30 |
zilmar
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35105e814e
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Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
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2023-10-05 09:54:41 +10:30 |
zilmar
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b7311cc611
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Core: Change Non memory load/store to not use tlb
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2023-10-05 09:32:45 +10:30 |
zilmar
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a975af0e3c
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Rsp: only use alignas for Visual Studio
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2023-09-28 16:18:39 +09:30 |
zilmar
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dd7ec63dd9
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Rsp: Change usage of alignas to try and fix android build
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2023-09-28 15:53:46 +09:30 |
zilmar
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7e249d22b1
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Try to fix android build
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2023-09-28 15:25:34 +09:30 |
zilmar
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46e6e54f24
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RSP: improve running RSP multithreaded
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2023-09-28 14:46:36 +09:30 |
zilmar
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15e6e460d2
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Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH
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2023-09-28 13:39:23 +09:30 |
zilmar
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3c52d8e2e3
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RSP: use vt instead of rt when using RSP_Vect
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2023-09-28 11:57:29 +09:30 |
zilmar
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0bd6a96118
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RSP: fix display of VRCP instruction
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2023-09-28 11:54:50 +09:30 |
zilmar
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b1240072c6
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RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core
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2023-09-28 11:53:57 +09:30 |
zilmar
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ac3e0f83d1
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Rsp: Use RSP Register Handler
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2023-09-28 11:52:06 +09:30 |
zilmar
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bd1ec4ff0f
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Core: Create a setting for RDRAM Size that plugins can read
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2023-09-28 07:29:11 +09:30 |
zilmar
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99417fc5d9
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Core: reset run event in CRSP_Plugin after rom close
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2023-09-28 07:19:20 +09:30 |
zilmar
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f817becf9c
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Core: Create a handler for RSP registers that is accessible to the core and the RSP
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2023-09-28 07:03:01 +09:30 |
zilmar
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03e13455f9
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Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot
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2023-09-28 06:39:39 +09:30 |
zilmar
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2caa457d02
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Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
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2023-09-22 11:01:46 +09:30 |
zilmar
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10d2b77d7c
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Core: Try to fix android build
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2023-09-21 20:13:41 +09:30 |
zilmar
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aadcca7528
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Core: Fix clang issue
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2023-09-21 18:40:27 +09:30 |
zilmar
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6307888be4
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Core: fix up exception generator functions
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2023-09-21 18:07:56 +09:30 |
zilmar
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32ff820a03
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RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH)
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2023-09-21 15:51:16 +09:30 |
zilmar
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dc95d2f7a4
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RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR)
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2023-09-21 15:44:07 +09:30 |
zilmar
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174e751a4a
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RSP: Fix up load ops (LUV, LHV, LFV, LTV)
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2023-09-21 15:30:07 +09:30 |
zilmar
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bdaf8cf78c
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RSP: Clean up store vector ops (SHV, SFV, STV, SWV)
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2023-09-21 15:25:45 +09:30 |
zilmar
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5dcc7e200f
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Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core
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2023-09-21 15:16:26 +09:30 |
zilmar
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42a944c660
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RSP: Setup option to run in a thread
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2023-09-21 14:25:07 +09:30 |
zilmar
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c4abebe201
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Core: Update <Project64-plugin-spec\ to <Project64-plugin-spec/
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2023-09-21 14:13:08 +09:30 |
zilmar
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f3d6d3fc7c
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Core: for tlb miss only use special address when address is not defined
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2023-09-14 18:39:15 +09:30 |
zilmar
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e0c125e837
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Core: Fix clang issue
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2023-09-14 16:33:20 +09:30 |
zilmar
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c02858c7a0
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Core: Add LLD opcode
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2023-09-14 16:31:37 +09:30 |
zilmar
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f559aed2ad
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Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
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2023-09-14 16:23:26 +09:30 |
zilmar
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ae4af8746b
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Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
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2023-09-14 13:09:11 +09:30 |
zilmar
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8b14b6d7d1
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Core: Move InitRegisters to register class
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2023-09-14 12:01:16 +09:30 |
zilmar
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a5a4873e84
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Core: Have CRegisters::DoAddressError to not directly modify program counter
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2023-09-14 11:37:21 +09:30 |
zilmar
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2d09178449
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Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions
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2023-09-14 11:15:42 +09:30 |
zilmar
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5da5dab3c5
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Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
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2023-09-14 11:09:28 +09:30 |
zilmar
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fcd7257adc
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Core: Change COP0 Status register to a struct breaking up the bits
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2023-09-14 10:23:36 +09:30 |
zilmar
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9ffd87168a
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Core: DisplayControlRegHandler::Read32 read more of the registers
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2023-09-14 09:40:11 +09:30 |
zilmar
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002f2e17c3
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RSP: Clean up code for vector multiple ops
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2023-09-07 11:54:36 +09:30 |
zilmar
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4e9a692449
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RSP: Add RSP_Vector_VRNDP
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2023-09-07 11:41:17 +09:30 |
zilmar
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0cadbe0f70
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RSP: Add clamp16
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2023-09-07 11:31:31 +09:30 |
zilmar
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af1c0c2b55
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RSP: Add Vmulq
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2023-09-07 11:30:15 +09:30 |
zilmar
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d468b863c2
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Rsp: add vnop for vnull
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2023-09-07 11:29:16 +09:30 |
zilmar
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8b71ef3bc1
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RSP: Add RSP_Vector_Reserved
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2023-09-07 11:23:35 +09:30 |
zilmar
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ab67374c8a
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RSP: Update the display of RSP opcodes in debugger
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2023-09-07 11:19:44 +09:30 |
zilmar
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4f74dc4bb0
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Rsp: Update display of vector in debugger
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2023-09-07 11:17:08 +09:30 |
zilmar
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ab03916a70
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Core: let the stack pointer equal end of rdram
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2023-09-07 11:13:54 +09:30 |
zilmar
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7199096748
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Core: Merge CheckFPUException into CheckFPUResult64
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2023-08-31 18:52:34 +09:30 |
zilmar
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91d1c6e237
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Core: Add fpu exceptions to COP1_S_MUL
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2023-08-31 11:09:48 +09:30 |
zilmar
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2f7a35613f
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Core: Add exception to COP1_S_SUB
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2023-08-31 10:54:41 +09:30 |
zilmar
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c28c6bb4a1
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Core: Add fpu exceptions to COP1_S_ADD
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2023-08-31 10:08:49 +09:30 |
zilmar
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416c85ecda
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Core: some code clean up of Load_FPR_ToTop
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2023-08-31 09:30:05 +09:30 |
zilmar
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2dcfcf250d
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Core: Do not force unmapping of fpr registers before CX86RegInfo::BeforeCallDirect(void)
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2023-08-31 09:28:23 +09:30 |
zilmar
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e49438cdab
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Core: Add exit reason exception
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2023-08-30 12:16:07 +09:30 |
zilmar
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703ad4049a
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PluginRSP: declare windows.h before asset.h
|
2023-08-30 12:15:36 +09:30 |
zilmar
|
41fa1fd5dd
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Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory
|
2023-08-30 11:35:53 +09:30 |
zilmar
|
625f532d73
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RSP: use __debugbreak not DebugBreak
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2023-08-24 10:44:45 +09:30 |
zilmar
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47f14016e6
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RSP: Set RSP_JumpTo before register in JALR, BLTZAL, BGEZAL
|
2023-08-24 10:35:51 +09:30 |
zilmar
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ae9912b068
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RSP: Clean up VCR
|
2023-08-24 10:31:26 +09:30 |
zilmar
|
7db5876927
|
RSP: Clean up VCL
|
2023-08-24 10:07:05 +09:30 |
zilmar
|
9dab3481ae
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RSP: Add class to wrap around RSP flag
|
2023-08-24 08:00:29 +09:30 |
zilmar
|
0cb43e0c33
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RSP: Remove flag to swap vector register endian
|
2023-08-24 07:04:35 +09:30 |
zilmar
|
d300dc002a
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Core: remove exception catch around RSP
|
2023-08-17 15:27:18 +09:30 |
zilmar
|
6884c8d2c9
|
Core: fix up how recompiler handles rounding
|
2023-08-17 15:24:57 +09:30 |
zilmar
|
a80860605d
|
RSP: fix up usage of Indx in recompiler
|
2023-08-17 14:38:51 +09:30 |
zilmar
|
3394be733f
|
RSP: Fix up AccurateEmulation for interpreter
|
2023-08-17 14:22:54 +09:30 |
zilmar
|
54be4d8135
|
Rsp: Add a rsp AccurateEmulation flag for new rsp work
|
2023-08-17 12:04:06 +09:30 |
zilmar
|
09ef426ac6
|
Rsp: Fix memory allocation of recompiler memory
|
2023-08-17 11:37:03 +09:30 |
zilmar
|
6b30c1ae6a
|
Rsp: Move Recompiler in to rsp-core
|
2023-08-17 08:59:22 +09:30 |
zilmar
|
1f0151e067
|
RSP: fix up clang formatting
|
2023-08-10 21:50:01 +09:30 |
zilmar
|
6bdc898248
|
RSP: fix LPV
|
2023-08-10 20:52:50 +09:30 |
zilmar
|
c6c0a4a6d2
|
RSP: fix LDV
|
2023-08-10 16:06:38 +09:30 |
zilmar
|
1d492262fd
|
RSP: use std::min for length calculation
|
2023-08-10 14:24:33 +09:30 |
zilmar
|
60192a7f33
|
RSP: Move more functionality in to rsp-core
|
2023-08-10 14:16:57 +09:30 |
zilmar
|
25e48405c5
|
RSP: Start to split out RSP in to core and UI for plugin
|
2023-08-10 10:27:11 +09:30 |
zilmar
|
bb5a16aaa2
|
RSP: Change RSP Registers to be an enum not define
|
2023-08-10 09:47:53 +09:30 |
zilmar
|
34d75780bf
|
Rsp: Update the element order in LSV, LLV, LRV
|
2023-08-03 17:32:40 +09:30 |
zilmar
|
a18f78679e
|
Rsp: Change the order of EleSpec
|
2023-08-03 17:29:55 +09:30 |
zilmar
|
05cd3a846b
|
Rsp: Update vmov
|
2023-08-03 17:27:58 +09:30 |
zilmar
|
b5db44c12d
|
Core: Get CheckFPUInput64Conv to return true on exception
|
2023-08-03 17:25:03 +09:30 |
zilmar
|
5ff45c43c4
|
Core: Get R4300iOp::CheckFPUInput64 to return true on exception
|
2023-08-03 17:11:56 +09:30 |
zilmar
|
bc1b027c94
|
Core: get CheckFPUInput32Conv to return true on exception
|
2023-08-03 16:24:54 +09:30 |