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277 Commits

Author SHA1 Message Date
zilmar 2014237ed6 Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler 2024-02-08 19:34:14 +10:30
zilmar ad1a2a2d9a Core: Update neg.s for the recompiler 2024-02-01 18:17:03 +10:30
zilmar b6671adf5d Core: Update abs.s for recompiler 2024-02-01 18:15:33 +10:30
zilmar bc3fe0fe16 Core: Handle FP Status Reg being mapped better 2024-01-25 18:46:39 +10:30
zilmar 7707f9c7b2 Core: Fix up mov.s and mov.d for correct behaviour in the recompiler 2024-01-25 16:25:06 +10:30
zilmar 272144dc37 Core: check timer on cop1 unusable 2024-01-25 16:23:03 +10:30
zilmar 7ed94b653e Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions 2024-01-18 17:09:27 +10:30
zilmar 4dc3e35bb4 Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions 2024-01-04 16:51:11 +10:30
zilmar f8089f565e Core: Unmap FPU_Float with writing to m_FPR_UDW 2024-01-04 14:40:42 +10:30
zilmar 552b8f744a Core: update Format_Name to match FPU_STATE 2024-01-04 13:11:21 +10:30
zilmar 6ca8333d39 Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions 2024-01-04 12:39:51 +10:30
zilmar c9d2bbd221 Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped 2024-01-04 12:37:06 +10:30
zilmar 0998f0ff0e Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer 2024-01-04 12:32:55 +10:30
zilmar 23cff4d7c5 Core: Add x86 asm opcode Jnp 2024-01-04 12:31:26 +10:30
zilmar 91a8a828d7 Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW 2024-01-04 12:01:21 +10:30
zilmar 320769d991 Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr 2024-01-04 10:33:07 +10:30
zilmar dafa1fb24d Core: Have COP1_W_CVT_S handle the initialization of exceptions 2023-12-28 11:19:06 +10:30
zilmar 17288c90c0 Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32 2023-12-28 10:23:18 +10:30
zilmar e2306e3541 Core: Get COP1_S_CVT_W to handle inexact 2023-12-28 09:21:53 +10:30
zilmar 8399fdb893 Core: Clear the Divide-by-zero flag 2023-12-21 21:24:33 +10:30
zilmar d14a639a62 Core: Implement COP1_S_DIV with fpu exceptions 2023-12-21 14:11:29 +10:30
zilmar 8e54ec8c8e Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis 2023-12-21 14:10:21 +10:30
zilmar b263ee10b0 Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0 2023-12-21 10:41:16 +10:30
zilmar 1810bfda5c Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops 2023-12-21 10:38:49 +10:30
zilmar 2c1610cfe2 Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode 2023-12-21 10:37:27 +10:30
zilmar 6610ae3058 Core: Have R4300iInstruction in CRecompilerOpsBase 2023-12-21 10:34:03 +10:30
zilmar c8e73ba18e Core: Handle unaligned SW exception in the recompiler 2023-12-14 23:04:26 +10:30
zilmar 972943cff7 Core: Allow LW to R0 be able to generate an exception 2023-12-14 17:21:52 +10:30
zilmar 89a6eaf9d1 Core: Add RecordLLAddress for 32bit register pointer 2023-12-14 13:52:15 +10:30
zilmar 67f5e4f854 Core: in LL for recompiler handle storing the address in COP[17] 2023-12-14 13:10:20 +10:30
zilmar 5fec3f8d31 Core: remove the global of g_TLB 2023-12-14 12:09:24 +10:30
zilmar c67f3f0e97 Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it 2023-12-14 11:18:07 +10:30
zilmar 4770d29ec0 Core: Get system events to be internal not global 2023-10-26 19:59:11 +10:30
zilmar d6a2ae80c1 Core: Remove SystemRegisters 2023-10-19 14:56:53 +10:30
zilmar 4d78f56aa2 Core: In R4300iOp have a member variable for system, reg, mmu 2023-10-19 12:31:26 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 7f42f70283 Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static 2023-10-19 10:28:25 +10:30
zilmar d3edbf6dda Core: move CInterpreterCPU into R4300iOp 2023-10-19 09:32:42 +10:30
zilmar 4e71221147 Core: Fix up FPU mode register location 2023-10-12 14:53:44 +10:30
zilmar 35105e814e Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss 2023-10-05 09:54:41 +10:30
zilmar b7311cc611 Core: Change Non memory load/store to not use tlb 2023-10-05 09:32:45 +10:30
zilmar f817becf9c Core: Create a handler for RSP registers that is accessible to the core and the RSP 2023-09-28 07:03:01 +09:30
zilmar 03e13455f9 Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot 2023-09-28 06:39:39 +09:30
zilmar 2caa457d02 Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue 
Update counter before mfc0 x, count
 2023-09-22 11:01:46 +09:30
zilmar ae4af8746b Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss 2023-09-14 13:09:11 +09:30
zilmar a5a4873e84 Core: Have CRegisters::DoAddressError to not directly modify program counter 2023-09-14 11:37:21 +09:30
zilmar 5da5dab3c5 Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC 2023-09-14 11:09:28 +09:30
zilmar fcd7257adc Core: Change COP0 Status register to a struct breaking up the bits 2023-09-14 10:23:36 +09:30
zilmar 91d1c6e237 Core: Add fpu exceptions to COP1_S_MUL 2023-08-31 11:09:48 +09:30
zilmar 2f7a35613f Core: Add exception to COP1_S_SUB 2023-08-31 10:54:41 +09:30