zilmar
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de1288bdca
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Core: remove try/catch around Interpreter cpu
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2023-11-30 21:15:14 +10:30 |
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zilmar
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df56964c96
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Android: Remove unneeded log call
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2023-11-30 21:13:27 +10:30 |
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zilmar
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5671f2b759
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Android: Update how Addu cause android studio was not sign extending result
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2023-11-30 21:12:53 +10:30 |
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zilmar
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01673dac8d
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Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
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2023-11-23 14:20:48 +10:30 |
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zilmar
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d47b49d4b5
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Core: Fix clang issue
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2023-11-16 18:24:47 +10:30 |
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zilmar
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542afc4514
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Core: remove some accidental added debug code
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2023-11-16 18:16:35 +10:30 |
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zilmar
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ee714e2462
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Core: On unmap base addresses reset to the correct address
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2023-11-16 18:14:15 +10:30 |
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zilmar
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8f4f434820
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Core: Get Fast tlb to just be 32bit
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2023-11-16 17:11:05 +10:30 |
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zilmar
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dcb6969067
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Core: Have entryHI use functions to set/get parts
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2023-11-16 09:19:24 +10:30 |
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zilmar
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a0130ff896
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Core: Convert %I64U to %llx
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2023-11-16 09:03:32 +10:30 |
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zilmar
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e6edbc6c82
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Fix clang formatting
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2023-10-27 10:14:21 +10:30 |
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zilmar
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4770d29ec0
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Core: Get system events to be internal not global
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2023-10-26 19:59:11 +10:30 |
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zilmar
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8f062975c3
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Core: improve DisplayControlRegHandler::Write32
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2023-10-19 19:28:38 +10:30 |
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zilmar
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d6a2ae80c1
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Core: Remove SystemRegisters
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2023-10-19 14:56:53 +10:30 |
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zilmar
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d58168bcb9
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Core: R4300iOp access the registers directly, not through CSystemRegisters
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2023-10-19 12:52:33 +10:30 |
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zilmar
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4d78f56aa2
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Core: In R4300iOp have a member variable for system, reg, mmu
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2023-10-19 12:31:26 +10:30 |
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zilmar
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ae0097550f
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Core: Make R4300iOp opcodes not static
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2023-10-19 11:43:32 +10:30 |
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zilmar
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7f42f70283
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Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
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2023-10-19 10:28:25 +10:30 |
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zilmar
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d3edbf6dda
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Core: move CInterpreterCPU into R4300iOp
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2023-10-19 09:32:42 +10:30 |
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zilmar
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d4dbc5a3f4
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Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
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2023-10-14 11:53:35 +10:30 |
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zilmar
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00c5057b17
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Core: Make sure precision is correct for COP1_D_SQRT
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2023-10-13 00:16:14 +10:30 |
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zilmar
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3a68d3d92a
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Core: LL/LLD store address
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2023-10-12 19:55:29 +10:30 |
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zilmar
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a6405cfa2d
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Core: Add masking around DPC_START_REG/DPC_END_REG
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2023-10-12 17:50:58 +10:30 |
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zilmar
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4e71221147
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Core: Fix up FPU mode register location
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2023-10-12 14:53:44 +10:30 |
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zilmar
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befa57924d
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Core: Fix clang compile issues
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2023-10-05 15:01:09 +10:30 |
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zilmar
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f73c3708a5
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Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
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2023-10-05 14:45:17 +10:30 |
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zilmar
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e74e8f6a23
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Core: Have load/store ops be able to use 64bit addresses
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2023-10-05 14:28:32 +10:30 |
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zilmar
|
9f07fe2aac
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Core: Get tlb addresses to be 64bit
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2023-10-05 13:42:31 +10:30 |
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zilmar
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4b844495b7
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Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
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2023-10-05 13:10:45 +10:30 |
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zilmar
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35105e814e
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Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
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2023-10-05 09:54:41 +10:30 |
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zilmar
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b7311cc611
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Core: Change Non memory load/store to not use tlb
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2023-10-05 09:32:45 +10:30 |
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zilmar
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ac3e0f83d1
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Rsp: Use RSP Register Handler
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2023-09-28 11:52:06 +09:30 |
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zilmar
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bd1ec4ff0f
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Core: Create a setting for RDRAM Size that plugins can read
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2023-09-28 07:29:11 +09:30 |
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zilmar
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f817becf9c
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Core: Create a handler for RSP registers that is accessible to the core and the RSP
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2023-09-28 07:03:01 +09:30 |
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zilmar
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03e13455f9
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Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot
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2023-09-28 06:39:39 +09:30 |
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zilmar
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2caa457d02
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Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
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2023-09-22 11:01:46 +09:30 |
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zilmar
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aadcca7528
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Core: Fix clang issue
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2023-09-21 18:40:27 +09:30 |
|
zilmar
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6307888be4
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Core: fix up exception generator functions
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2023-09-21 18:07:56 +09:30 |
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zilmar
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42a944c660
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RSP: Setup option to run in a thread
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2023-09-21 14:25:07 +09:30 |
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zilmar
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f3d6d3fc7c
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Core: for tlb miss only use special address when address is not defined
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2023-09-14 18:39:15 +09:30 |
|
zilmar
|
e0c125e837
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Core: Fix clang issue
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2023-09-14 16:33:20 +09:30 |
|
zilmar
|
c02858c7a0
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Core: Add LLD opcode
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2023-09-14 16:31:37 +09:30 |
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zilmar
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f559aed2ad
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Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
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2023-09-14 16:23:26 +09:30 |
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zilmar
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ae4af8746b
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Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
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2023-09-14 13:09:11 +09:30 |
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zilmar
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8b14b6d7d1
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Core: Move InitRegisters to register class
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2023-09-14 12:01:16 +09:30 |
|
zilmar
|
a5a4873e84
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Core: Have CRegisters::DoAddressError to not directly modify program counter
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2023-09-14 11:37:21 +09:30 |
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zilmar
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2d09178449
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Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions
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2023-09-14 11:15:42 +09:30 |
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zilmar
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5da5dab3c5
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Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
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2023-09-14 11:09:28 +09:30 |
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zilmar
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fcd7257adc
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Core: Change COP0 Status register to a struct breaking up the bits
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2023-09-14 10:23:36 +09:30 |
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zilmar
|
9ffd87168a
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Core: DisplayControlRegHandler::Read32 read more of the registers
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2023-09-14 09:40:11 +09:30 |