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appveyor

feature/cached-interp

feature/dynarec

feature/sio-dolphin

master

medusa

optimization/arm-inline

optimization/arm-noinline

optimization/cpu-alu

optimization/dma-caching

optimization/invert-window

optimization/ls-reduce

optimization/negative-clock2

optimization/page-align

optimization/staging

optimization/thumb-notrunc

optimization/unify-barrel

optimization/video

optimization/video-tests/affine1

optimization/video-tests/affine2

optimization/video-tests/affine3

optimization/video-tests/localy

optimization/video-tests/obj-postprocess

port/crucible

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0.1.0

0.1.1

0.10.0

0.10.1

0.10.2

0.10.3

0.10.4

0.2.0

0.2.1

0.3.0

0.3.1

0.3.2

0.4.0

0.4.1

0.5.0

0.5.1

0.5.2

0.6-b1

0.6.0

0.6.1

0.6.2

0.6.3

0.7-b1

0.7.0

0.7.1

0.7.2

0.7.3

0.8-b1

0.8.0

0.8.1

0.8.2

0.8.3

0.8.4

0.9.0

0.9.1

0.9.2

0.9.3

medusa-a1

medusa-a2

c8f85a657e Implement STR(3) Jeffrey Pfau 2013-04-12 21:48:30 -0700
3e57e46046 Implement ADD(2) Jeffrey Pfau 2013-04-12 21:48:19 -0700
b5182915d7 Command to break into attached debugger Jeffrey Pfau 2013-04-12 21:27:43 -0700
a7bc99c846 Implement LDR(3) Jeffrey Pfau 2013-04-12 20:09:27 -0700
57f2cccacf Implement STRH(1) Jeffrey Pfau 2013-04-12 20:06:58 -0700
21ee7946f1 Implement LSL(1) Jeffrey Pfau 2013-04-12 20:00:14 -0700
71c68fe79f Implement ADD(6) Jeffrey Pfau 2013-04-12 19:59:55 -0700
21df1c48c2 Implement MOV(1) Jeffrey Pfau 2013-04-12 02:44:04 -0700
9ab3b0c20a Implement ADD(7)/SUB(4) Jeffrey Pfau 2013-04-12 02:22:37 -0700
1ac7f0eb15 Implement MOV(3) Jeffrey Pfau 2013-04-12 02:15:47 -0700
37ce1383fc Set bits in MSR properly Jeffrey Pfau 2013-04-12 02:10:09 -0700
6097890251 Print proper register Jeffrey Pfau 2013-04-12 02:04:51 -0700
688af6cdee Add some basic input to the debugger Jeffrey Pfau 2013-04-12 02:03:11 -0700
1db7f5b179 Initial debugger Jeffrey Pfau 2013-04-12 01:32:43 -0700
b07e052698 Move CMakeList Jeffrey Pfau 2013-04-11 23:58:13 -0700
09455b50d3 Add linenoise module Jeffrey Pfau 2013-04-11 23:52:51 -0700
d90d7d1899 Implement BL Jeffrey Pfau 2013-04-11 03:14:09 -0700
133d574667 Implement LDMIA/STMIA/PUSH/POP Jeffrey Pfau 2013-04-11 03:01:07 -0700
1616ec83a2 Stub out incomplete addressing mode 1 opcodes Jeffrey Pfau 2013-04-11 02:13:35 -0700
4fbed66bdb Start fleshing out addressing mode 1 Jeffrey Pfau 2013-04-11 01:32:30 -0700
d278429b43 Implement BX Jeffrey Pfau 2013-04-11 00:14:12 -0700
a511df7920 Put stub definitions in all of Thumb Jeffrey Pfau 2013-04-10 23:38:18 -0700
7e5de27f43 Add ability to run Thumb code Jeffrey Pfau 2013-04-10 23:34:50 -0700
9a0d14645b Log stubs Jeffrey Pfau 2013-04-10 22:52:46 -0700
9a7f0f4a74 Stub out BL, finishing Thumb table Jeffrey Pfau 2013-04-10 21:11:05 -0700
87863ad97a Stub out B Jeffrey Pfau 2013-04-10 21:09:22 -0700
cbc17ad77e Stub out SWI Jeffrey Pfau 2013-04-10 21:05:19 -0700
e89f49459a Stub out conditional branches Jeffrey Pfau 2013-04-10 21:04:41 -0700
d5adcac319 Stub out LDMIA/STMIA Jeffrey Pfau 2013-04-10 20:58:05 -0700
0db11ec6bb Stub out BKPT (not in ARMv4T, but still useful) Jeffrey Pfau 2013-04-10 20:50:56 -0700
5e78400a25 Stub out POP/PUSH Jeffrey Pfau 2013-04-10 00:00:24 -0700
99d0b76f3b Stub out ADD7 and SUB4 Jeffrey Pfau 2013-04-09 23:47:37 -0700
08065d865d Stub out ADD from PC and SP Jeffrey Pfau 2013-04-09 23:45:08 -0700
28ecc97671 Stub out LDR/STR from SP Jeffrey Pfau 2013-04-09 23:37:28 -0700
e3818cf7b6 Stub out more load/stores with immediates Jeffrey Pfau 2013-04-09 23:34:25 -0700
39c776eb37 Stub out more load/store format 2 Jeffrey Pfau 2013-04-09 23:27:37 -0700
5165e0131e Put in missing BX Jeffrey Pfau 2013-04-09 23:16:30 -0700
f42c8d111e Stub out STR2 Jeffrey Pfau 2013-04-09 23:00:31 -0700
11de611fd2 Stub out LDR3 Jeffrey Pfau 2013-04-09 22:57:24 -0700
5e18eabd04 Stub out format 8 Jeffrey Pfau 2013-04-09 22:51:21 -0700
be021605bc Define data format 5 Jeffrey Pfau 2013-04-09 22:35:51 -0700
e577df2142 Fix data format 3 Jeffrey Pfau 2013-04-09 22:35:38 -0700
d3abd2dc63 Minor ROM access optimization Jeffrey Pfau 2013-04-09 22:20:35 -0700
027e27caa4 Add data form 3 Jeffrey Pfau 2013-04-09 04:20:14 -0700
56c3685ba6 ADD/SUB 1 stubs Jeffrey Pfau 2013-04-09 03:20:32 -0700
2618c39a5d Macro-insanity for Thumb Jeffrey Pfau 2013-04-09 03:15:50 -0700
76dbfce3c3 Start filling in THUMB table with insane preprocessor tricks Jeffrey Pfau 2013-04-09 02:57:24 -0700
70eb3634a0 Fix warnings + LDR[B]T/STR[B]T Jeffrey Pfau 2013-04-08 03:14:18 -0700
9a1fb100c7 Load/store working RAM Jeffrey Pfau 2013-04-08 03:13:37 -0700
93a2f16066 Loading 8/16 bits from ROM Jeffrey Pfau 2013-04-08 02:13:40 -0700
67c00f378a Ensure CPSR privilege gets updated in MSR Jeffrey Pfau 2013-04-08 00:21:28 -0700
37ad6218da Don't double-execute AL instructions Jeffrey Pfau 2013-04-08 00:17:54 -0700
4f3e77c87e Implement MSR Jeffrey Pfau 2013-04-08 00:15:16 -0700
4bba75dd0a Separate out ISA files Jeffrey Pfau 2013-04-07 21:15:32 -0700
b02fdd3dda Remove inline conditions and add ARM specialization Jeffrey Pfau 2013-04-07 20:37:48 -0700
186068adfe Start filling in ARMBoard Jeffrey Pfau 2013-04-07 13:25:45 -0700
120b85713d Mode switching Jeffrey Pfau 2013-04-07 02:36:41 -0700
bda71cafc2 ALU instructions can write to PC Jeffrey Pfau 2013-04-07 02:01:14 -0700
6e3a9a9508 Fix writing to PC Jeffrey Pfau 2013-04-07 01:57:04 -0700
68f2eed84d Mini-test Jeffrey Pfau 2013-04-07 01:39:49 -0700
9575e7f0d2 Fix B Jeffrey Pfau 2013-04-07 01:39:08 -0700
0e2394e7d5 De-inline ARMStep Jeffrey Pfau 2013-04-07 01:46:48 -0700
b23f1ee3e3 GBA ROM loading Jeffrey Pfau 2013-04-07 01:46:28 -0700
340d3ce6a7 Implement B Jeffrey Pfau 2013-04-06 20:16:14 -0700
5c7b4a98c6 Load from ARM table now that we have one Jeffrey Pfau 2013-04-06 20:06:51 -0700
6bd7a5ee53 Fill remainder of table Jeffrey Pfau 2013-04-06 20:01:32 -0700
7a0fb72e7e Stub out SWI Jeffrey Pfau 2013-04-06 19:58:01 -0700
d620357ac8 Stub out coprocessor Jeffrey Pfau 2013-04-06 19:52:45 -0700
5dd2379dd5 Cleanup Jeffrey Pfau 2013-04-06 19:38:14 -0700
f2a1257fbb Stub out branch instructions Jeffrey Pfau 2013-04-06 19:22:14 -0700
1858dfeb1c Stub out LDM/STM Jeffrey Pfau 2013-04-06 18:41:36 -0700
7b82cc0040 Fill in LDR/STR block Jeffrey Pfau 2013-04-06 13:05:53 -0700
befba57fe6 Simple error checking Jeffrey Pfau 2013-04-06 04:34:19 -0700
9efc945f1b Add store callbacks Jeffrey Pfau 2013-04-06 04:20:44 -0700
96da9c7ef1 Partially implement LDR/STR and friends Jeffrey Pfau 2013-04-06 04:16:27 -0700
92e74a78e1 Apparently I can't count to 8 Jeffrey Pfau 2013-04-06 02:49:54 -0700
cb2469c4f4 Filler for more instructions Jeffrey Pfau 2013-04-06 00:32:01 -0700
a01fc986a3 Begin GBA structure Jeffrey Pfau 2013-04-05 02:17:22 -0700
cd07dee7b1 Implement immediate shifter Jeffrey Pfau 2013-04-05 00:43:47 -0700
c07df4a337 Fill in immediates Jeffrey Pfau 2013-04-04 03:12:22 -0700
63f6f53a80 Implement BIC, MOV, MVN, ORR Jeffrey Pfau 2013-04-04 02:42:17 -0700
dbee1e871e Add stubs, including for illegal instructions Jeffrey Pfau 2013-04-04 02:36:53 -0700
e093960316 Fill in more opcodes, implement CMN, CMP, TEQ, TST Jeffrey Pfau 2013-04-04 02:31:32 -0700
fd4ee12eb5 Implement ADD, ADC, RSB, RSC, SUB Jeffrey Pfau 2013-04-04 02:04:51 -0700
c1a8042db4 Fill in more opcodes, implement EOR Jeffrey Pfau 2013-04-04 01:27:51 -0700
4025bf89f2 Add boilerplate for instructions Jeffrey Pfau 2013-04-04 00:46:50 -0700
bf72532715 Add more framework for loading instructions Jeffrey Pfau 2013-04-03 22:34:49 -0700
009bef870c Initial commit Jeffrey Pfau 2013-04-03 22:12:15 -0700