mirror of https://github.com/mgba-emu/mgba.git
Add boilerplate for instructions
This commit is contained in:
Jeffrey Pfau
parent
bf72532715
commit
4025bf89f2
191
src/arm.c
191
src/arm.c
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@ -1,10 +1,20 @@
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#include "arm.h"
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static void _ARMSetMode(struct ARMCore*, enum ExecutionMode);
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static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory*, uint32_t address);
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static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory*, uint32_t address);
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static inline void _ARMSetMode(struct ARMCore*, enum ExecutionMode);
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static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
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static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
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static void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
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static inline void _ARMReadCPSR(struct ARMCore* cpu) {
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_ARMSetMode(cpu, cpu->cpsr.t);
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}
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static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
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return mode != MODE_SYSTEM && mode != MODE_USER;
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}
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static const ARMInstruction armTable[0x100000];
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static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
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if (executionMode == cpu->executionMode) {
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return;
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}
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@ -23,13 +33,15 @@ static void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
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}
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}
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static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address) {
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int32_t opcode = memory->load32(memory, address);
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static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
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uint32_t opcode = memory->load32(memory, address);
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*opcodeOut = opcode;
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return 0;
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}
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static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory* memory, uint32_t address) {
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static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
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uint16_t opcode = memory->loadU16(memory, address);
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*opcodeOut = opcode;
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return 0;
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}
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@ -39,7 +51,7 @@ void ARMInit(struct ARMCore* cpu) {
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cpu->gprs[i] = 0;
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}
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cpu->cpsr.packed = 0;
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cpu->cpsr.packed = MODE_SYSTEM;
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cpu->spsr.packed = 0;
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cpu->cyclesToEvent = 0;
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@ -58,7 +70,164 @@ void ARMAssociateMemory(struct ARMCore* cpu, struct ARMMemory* memory) {
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cpu->memory = memory;
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}
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void ARMCycle(struct ARMCore* cpu) {
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inline void ARMCycle(struct ARMCore* cpu) {
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// TODO
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ARMInstruction instruction = cpu->loadInstruction(cpu->memory, cpu->gprs[ARM_PC] - cpu->instructionWidth);
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}
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uint32_t opcode;
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ARMInstruction instruction = cpu->loadInstruction(cpu->memory, cpu->gprs[ARM_PC] - cpu->instructionWidth, &opcode);
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cpu->gprs[ARM_PC] += cpu->instructionWidth;
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instruction(cpu, opcode);
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}
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// Instruction definitions
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// Beware pre-processor antics
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#define ARM_CARRY_FROM ((((M) | (N)) >> 31) && !((D) >> 31)))
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#define ARM_COND_EQ (cpu->cpsr.z)
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#define ARM_COND_NE (!cpu->cpsr.z)
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#define ARM_COND_CS (cpu->cpsr.c)
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#define ARM_COND_CC (!cpu->cpsr.c)
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#define ARM_COND_MI (cpu->cpsr.n)
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#define ARM_COND_PL (!cpu->cpsr.n)
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#define ARM_COND_VS (cpu->cpsr.v)
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#define ARM_COND_VC (!cpu->cpsr.v)
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#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
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#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
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#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
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#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
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#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
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#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
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#define ARM_COND_AL 1
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#define ARM_ADDITION_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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cpu->cpsr.n = (D) >> 31; \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
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} \
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#define ARM_NEUTRAL_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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cpu->cpsr.n = (D) >> 31; \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = cpu->shifterCarryOut; \
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} \
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// TODO: shifter
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#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, S, S_BODY, BODY) \
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static void _ARMInstruction ## NAME ## S ## COND (struct ARMCore* cpu, uint32_t opcode) { \
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if (!COND_BODY) { \
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return; \
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} \
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int rd = (opcode >> 12) & 0xF; \
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int rn = (opcode >> 16) & 0xF; \
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BODY; \
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S_BODY; \
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}
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, S, S_BODY, BODY)
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DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand; \
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)
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#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
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_ARMInstruction ## NAME ## COND
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#define DO_16(DIRECTIVE) \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE \
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#define DO_128(DIRECTIVE) \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE), \
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DO_16(DIRECTIVE) \
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// TODO: MUL
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#define DECLARE_ARM_ALU_MUL_BLOCK(COND, ALU, MUL) \
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DO_128(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(0), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU))
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#define DECLARE_COND_BLOCK(COND) \
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DECLARE_ARM_ALU_MUL_BLOCK(COND, AND, MUL), \
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DECLARE_ARM_ALU_MUL_BLOCK(COND, ANDS, MULS)
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static const ARMInstruction armTable[0x100000] = {
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DECLARE_COND_BLOCK(EQ),
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DECLARE_COND_BLOCK(NE),
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DECLARE_COND_BLOCK(CS),
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DECLARE_COND_BLOCK(CC),
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DECLARE_COND_BLOCK(MI),
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DECLARE_COND_BLOCK(PL),
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DECLARE_COND_BLOCK(VS),
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DECLARE_COND_BLOCK(VC),
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DECLARE_COND_BLOCK(HI),
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DECLARE_COND_BLOCK(LS),
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DECLARE_COND_BLOCK(GE),
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DECLARE_COND_BLOCK(LT),
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DECLARE_COND_BLOCK(GT),
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DECLARE_COND_BLOCK(LE),
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DECLARE_COND_BLOCK(AL)
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};
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@ -40,15 +40,14 @@ enum ExecutionVector {
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};
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struct ARMCore;
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typedef void (*ARMInstruction)(struct ARMCore*);
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typedef void (*ARMInstruction)(struct ARMCore*, uint32_t opcode);
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union PSR {
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struct {
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int exec : 4;
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enum PrivilegeMode priv : 5;
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int t : 1;
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int f : 1;
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int i : 1;
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int a : 1;
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int : 20;
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int v : 1;
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int c : 1;
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@ -81,7 +80,7 @@ struct ARMCore {
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int instructionWidth;
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ARMInstruction (*loadInstruction)(struct ARMMemory*, uint32_t address);
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ARMInstruction (*loadInstruction)(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
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enum ExecutionMode executionMode;
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struct ARMMemory* memory;
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@ -91,6 +90,6 @@ struct ARMCore {
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void ARMInit(struct ARMCore* cpu);
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void ARMAssociateMemory(struct ARMCore* cpu, struct ARMMemory* memory);
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void ARMCycle(struct ARMCore* cpu);
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inline void ARMCycle(struct ARMCore* cpu);
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#endif
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