mirror of https://github.com/mgba-emu/mgba.git
Start fleshing out addressing mode 1
This commit is contained in:
Jeffrey Pfau
parent
d278429b43
commit
4fbed66bdb
154
src/isa-arm.c
154
src/isa-arm.c
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@ -10,8 +10,61 @@ enum {
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};
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// Addressing mode 1
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static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
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// TODO
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static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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int immediate = (opcode & 0x00000F80) >> 7;
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if (!immediate) {
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cpu->shifterOperand = cpu->gprs[rm];
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else {
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cpu->shifterOperand = cpu->gprs[rm] << immediate;
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cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
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}
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}
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static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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}
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static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
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cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
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}
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}
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static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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}
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static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = cpu->gprs[rm] >> immediate;
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cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
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} else {
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cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
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cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
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}
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}
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static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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}
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static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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int immediate = (opcode & 0x00000F80) >> 7;
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}
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static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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}
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static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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@ -195,14 +248,35 @@ void ARMStep(struct ARMCore* cpu) {
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})
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
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#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, _barrelShift, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY)
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#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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@ -467,14 +541,21 @@ DEFINE_INSTRUCTION_ARM(SWI, ARM_STUB)
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
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#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU)), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
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#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
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@ -535,7 +616,22 @@ DEFINE_INSTRUCTION_ARM(SWI, ARM_STUB)
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DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWP, STRHP, ILL, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
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@ -554,9 +650,39 @@ DEFINE_INSTRUCTION_ARM(SWI, ARM_STUB)
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWPB, STRHIP, ILL, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MSR, ILL, STRHIPW, ILL, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
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