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Remove inline conditions and add ARM specialization

This commit is contained in:
Jeffrey Pfau 2013-04-07 20:37:48 -07:00
parent 186068adfe
commit b02fdd3dda
2 changed files with 359 additions and 325 deletions
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681
src/arm.c
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@ -92,7 +92,7 @@ static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
}
}
static const ARMInstruction _armTable[0x10000];
static const ARMInstruction _armTable[0x1000];
static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
if (executionMode == cpu->executionMode) {
@ -103,20 +103,16 @@ static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode execution
switch (executionMode) {
case MODE_ARM:
cpu->cpsr.t = 0;
cpu->instructionWidth = WORD_SIZE_ARM;
cpu->loadInstruction = _ARMLoadInstructionARM;
break;
case MODE_THUMB:
cpu->cpsr.t = 1;
cpu->instructionWidth = WORD_SIZE_THUMB;
cpu->loadInstruction = _ARMLoadInstructionThumb;
}
}
static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
uint32_t opcode = memory->load32(memory, address);
*opcodeOut = opcode;
return _armTable[((opcode >> 16) & 0xFFF0) | ((opcode >> 4) & 0x000F)];
return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
}
static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
@ -169,22 +165,6 @@ void ARMReset(struct ARMCore* cpu) {
cpu->board->reset(cpu->board);
}
void ARMStep(struct ARMCore* cpu) {
// TODO
uint32_t opcode;
ARMInstruction instruction = cpu->loadInstruction(cpu->memory, cpu->gprs[ARM_PC] - cpu->instructionWidth, &opcode);
cpu->gprs[ARM_PC] += cpu->instructionWidth;
instruction(cpu, opcode);
}
// Instruction definitions
// Beware pre-processor antics
#define ARM_CARRY_FROM(M, N, D) ((ARM_SIGN((M) | (N))) && !(ARM_SIGN(D)))
#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
#define ARM_COND_EQ (cpu->cpsr.z)
#define ARM_COND_NE (!cpu->cpsr.z)
#define ARM_COND_CS (cpu->cpsr.c)
@ -201,8 +181,104 @@ void ARMStep(struct ARMCore* cpu) {
#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
#define ARM_COND_AL 1
void ARMStep(struct ARMCore* cpu) {
// TODO
uint32_t opcode;
ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
int condition = opcode >> 28;
if (condition == 0xE) {
instruction(cpu, opcode);
} else {
switch (condition) {
case 0x0:
if (!ARM_COND_EQ) {
return;
}
break;
case 0x1:
if (!ARM_COND_NE) {
return;
}
break;
case 0x2:
if (!ARM_COND_CS) {
return;
}
break;
case 0x3:
if (!ARM_COND_CC) {
return;
}
break;
case 0x4:
if (!ARM_COND_MI) {
return;
}
break;
case 0x5:
if (!ARM_COND_PL) {
return;
}
break;
case 0x6:
if (!ARM_COND_VS) {
return;
}
break;
case 0x7:
if (!ARM_COND_VC) {
return;
}
break;
case 0x8:
if (!ARM_COND_HI) {
return;
}
break;
case 0x9:
if (!ARM_COND_LS) {
return;
}
break;
case 0xA:
if (!ARM_COND_GE) {
return;
}
break;
case 0xB:
if (!ARM_COND_LT) {
return;
}
break;
case 0xC:
if (!ARM_COND_GT) {
return;
}
break;
case 0xD:
if (!ARM_COND_GE) {
return;
}
break;
default:
break;
}
}
instruction(cpu, opcode);
}
// Instruction definitions
// Beware pre-processor antics
#define ARM_CARRY_FROM(M, N, D) ((ARM_SIGN((M) | (N))) && !(ARM_SIGN(D)))
#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
#define ARM_WRITE_PC \
cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -cpu->instructionWidth) + cpu->instructionWidth
cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM
#define ARM_ADDITION_S(M, N, D) \
if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
@ -254,31 +330,11 @@ void ARMStep(struct ARMCore* cpu) {
#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
#define DEFINE_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, BODY) \
static void _ARMInstruction ## NAME ## COND (struct ARMCore* cpu, uint32_t opcode) { \
if (!COND_BODY) { \
return; \
} \
#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
BODY; \
}
#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY)
#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
DEFINE_INSTRUCTION_ARM(NAME, \
int rd = (opcode >> 12) & 0xF; \
@ -481,8 +537,8 @@ DEFINE_INSTRUCTION_ARM(MSRI,)
DEFINE_INSTRUCTION_ARM(MRSI,)
DEFINE_INSTRUCTION_ARM(SWI,)
#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
_ARMInstruction ## NAME ## COND
#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
EMITTER ## NAME
#define DO_8(DIRECTIVE) \
DIRECTIVE, \
@ -504,294 +560,275 @@ DEFINE_INSTRUCTION_ARM(SWI,)
LEFT, \
RIGHT
#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ALU) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)), \
DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I))
#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
#define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
DECLARE_INSTRUCTION_ARM(COND, ALU), \
DECLARE_INSTRUCTION_ARM(COND, EX1), \
DECLARE_INSTRUCTION_ARM(COND, ALU), \
DECLARE_INSTRUCTION_ARM(COND, EX2), \
DECLARE_INSTRUCTION_ARM(COND, ALU), \
DECLARE_INSTRUCTION_ARM(COND, EX3), \
DECLARE_INSTRUCTION_ARM(COND, ALU), \
DECLARE_INSTRUCTION_ARM(COND, EX4)
#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU)), \
DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, NAME, P, U, W) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)), \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W))
#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
#define DECLARE_ARM_LOAD_STORE_BLOCK(COND, NAME, P, U, W) \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSL_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _ASR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSL_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _ASR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL)
#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, NAME, MODE, W) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W)), \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W))
#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
#define DECLARE_ARM_BRANCH_BLOCK(COND, NAME) \
DO_256(DECLARE_INSTRUCTION_ARM(COND, NAME))
#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
// TODO: Support coprocessors
#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, NAME, P, U, W, N) \
#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
DO_8(0), \
DO_8(0)
#define DECLARE_ARM_COPROCESSOR_BLOCK(COND, NAME1, NAME2) \
#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
DO_8(DO_8(DO_INTERLACE(0, 0))), \
DO_8(DO_8(DO_INTERLACE(0, 0)))
#define DECLARE_ARM_SWI_BLOCK(COND) \
DO_256(DECLARE_INSTRUCTION_ARM(COND, SWI))
#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
#define DECLARE_COND_BLOCK(COND) \
DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
DECLARE_INSTRUCTION_ARM(COND, MSR), \
DECLARE_INSTRUCTION_ARM(COND, BX), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, STRHPW), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_INSTRUCTION_ARM(COND, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHIPW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRHPU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRHPUW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRHIPU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRHIPUW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EORS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUB), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUBS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSB), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSBS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADD), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADDS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TST), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TEQ), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMP), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMN), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOV), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOVS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRBT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRBT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRBT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRBT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W), \
DECLARE_ARM_BRANCH_BLOCK(COND, B), \
DECLARE_ARM_BRANCH_BLOCK(COND, BL), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
DECLARE_ARM_COPROCESSOR_BLOCK(COND, CDP, MCR), \
DECLARE_ARM_SWI_BLOCK(COND)
#define DECLARE_EMITTER_BLOCK(EMITTER) \
DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWP, STRHP, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWPB, STRHIP, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MSR, ILL, STRHIPW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
DECLARE_ARM_SWI_BLOCK(EMITTER)
#define DECLARE_EMPTY_BLOCK \
DO_8(DO_256(0)), \
DO_8(DO_256(0))
static const ARMInstruction _armTable[0x10000] = {
DECLARE_COND_BLOCK(EQ),
DECLARE_COND_BLOCK(NE),
DECLARE_COND_BLOCK(CS),
DECLARE_COND_BLOCK(CC),
DECLARE_COND_BLOCK(MI),
DECLARE_COND_BLOCK(PL),
DECLARE_COND_BLOCK(VS),
DECLARE_COND_BLOCK(VC),
DECLARE_COND_BLOCK(HI),
DECLARE_COND_BLOCK(LS),
DECLARE_COND_BLOCK(GE),
DECLARE_COND_BLOCK(LT),
DECLARE_COND_BLOCK(GT),
DECLARE_COND_BLOCK(LE),
DECLARE_COND_BLOCK(AL),
DECLARE_EMPTY_BLOCK
static const ARMInstruction _armTable[0x1000] = {
DECLARE_EMITTER_BLOCK(_ARMInstruction)
};

3
src/arm.h
View File

@ -97,9 +97,6 @@ struct ARMCore {
int32_t shifterOperand;
int32_t shifterCarryOut;
int instructionWidth;
ARMInstruction (*loadInstruction)(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
enum ExecutionMode executionMode;
enum PrivilegeMode privilegeMode;