mirror of https://github.com/mgba-emu/mgba.git
Partially implement LDR/STR and friends
This commit is contained in:
Jeffrey Pfau
parent
92e74a78e1
commit
96da9c7ef1
171
src/arm.c
171
src/arm.c
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@ -15,6 +15,7 @@ static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
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return mode != MODE_SYSTEM && mode != MODE_USER;
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}
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// Addressing mode 1
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static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
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// TODO
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}
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@ -153,6 +154,24 @@ inline void ARMCycle(struct ARMCore* cpu) {
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cpu->cpsr.c = cpu->shifterCarryOut; \
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}
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#define ADDR_MODE_2_ADDRESS (address)
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#define ADDR_MODE_2_RN (cpu->gprs[rn])
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#define ADDR_MODE_2_RM (cpu->gprs[rm])
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#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
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#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
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#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
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#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
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#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
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#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
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#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
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#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
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#define ADDR_MODE_3_RN ADDR_MODE_2_RN
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#define ADDR_MODE_3_RM ADDR_MODE_2_RM
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#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
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#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
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#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
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#define DEFINE_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, BODY) \
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static void _ARMInstruction ## NAME ## COND (struct ARMCore* cpu, uint32_t opcode) { \
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if (!COND_BODY) { \
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@ -193,27 +212,44 @@ inline void ARMCycle(struct ARMCore* cpu) {
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
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#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME ## ADDRESS, \
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BODY;)
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#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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uint32_t address; \
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int rn = (opcode >> 16) & 0xF; \
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int rd = (opcode >> 12) & 0xF; \
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int rm = opcode & 0xF; \
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address = ADDRESS; \
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BODY; \
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WRITEBACK;)
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// TODO: shifters
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#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, W, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, U, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, UW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, P, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PU, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PUW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, I, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IU, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IUW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IP, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPU, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPUW, BODY)
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
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#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
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// Begin ALU definitions
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@ -289,14 +325,14 @@ DEFINE_INSTRUCTION_ARM(UMULLS,)
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// Begin load/store definitions
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRH,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRSB,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRSH,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRH,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
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DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
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DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
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DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
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DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
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DEFINE_INSTRUCTION_ARM(SWP,)
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DEFINE_INSTRUCTION_ARM(SWPB,)
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@ -342,6 +378,23 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
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DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)) \
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DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W))
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#define LDRHW ILL
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#define LDRSBW ILL
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#define LDRSHW ILL
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#define LDRHIW ILL
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#define LDRSBIW ILL
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#define LDRSHIW ILL
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#define LDRHUW ILL
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#define LDRSBUW ILL
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#define LDRSHUW ILL
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#define LDRHIUW ILL
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#define LDRSBIUW ILL
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#define LDRSHIUW ILL
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#define STRHIW ILL
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#define STRHIUW ILL
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#define STRHUW ILL
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#define STRHW ILL
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#define DECLARE_COND_BLOCK(COND) \
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DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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@ -407,38 +460,38 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)//, \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , W), \
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@ -64,6 +64,10 @@ struct ARMMemory {
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uint16_t (*loadU16)(struct ARMMemory*, uint32_t address);
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int8_t (*load8)(struct ARMMemory*, uint32_t address);
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uint8_t (*loadU8)(struct ARMMemory*, uint32_t address);
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void (*store32)(struct ARMMemory*, uint32_t address, int32_t value);
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void (*store16)(struct ARMMemory*, uint32_t address, int16_t value);
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void (*store8)(struct ARMMemory*, uint32_t address, int8_t value);
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};
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struct ARMBoard {
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