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Stub out LDM/STM

This commit is contained in:
Jeffrey Pfau 2013-04-06 18:41:36 -07:00
parent 7b82cc0040
commit 1858dfeb1c
1 changed files with 64 additions and 18 deletions
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82
src/arm.c
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@ -257,6 +257,29 @@ inline void ARMCycle(struct ARMCore* cpu) {
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
// TODO
#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
DEFINE_INSTRUCTION_ARM(NAME, \
BODY;)
#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
// Begin ALU definitions
DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
@ -344,6 +367,9 @@ DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRBT,)
DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRT,)
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,)
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,)
DEFINE_INSTRUCTION_ARM(SWP,)
DEFINE_INSTRUCTION_ARM(SWPB,)
@ -406,6 +432,10 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
DECLARE_INSTRUCTION_ARM(COND, ILL)
#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, NAME, MODE, W) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W)), \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W))
#define LDRHW ILL
#define LDRSBW ILL
#define LDRSHW ILL
@ -551,23 +581,39 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W)//, \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, ), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, W), \
// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, W), \
DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IA, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IA, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, ), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W)//, \
// DECLARE_ARM_BRANCH_BLOCK(COND, B), \
// DECLARE_ARM_BRANCH_BLOCK(COND, BL), \
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \
@ -622,4 +668,4 @@ static const ARMInstruction armTable[0x10000] = {
DECLARE_COND_BLOCK(LE),
DECLARE_COND_BLOCK(AL)//,
//DECLARE_EMPTY_BLOCK
};
};