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mgba
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52 Commits 36 Branches 40 Tags 59 MiB
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52 Commits

Author SHA1 Message Date
Jeffrey Pfau 5165e0131e Put in missing BX 2013-04-09 23:16:30 -07:00
Jeffrey Pfau f42c8d111e Stub out STR2 2013-04-09 23:00:31 -07:00
Jeffrey Pfau 11de611fd2 Stub out LDR3 2013-04-09 22:57:24 -07:00
Jeffrey Pfau 5e18eabd04 Stub out format 8 2013-04-09 22:51:21 -07:00
Jeffrey Pfau be021605bc Define data format 5 2013-04-09 22:35:51 -07:00
Jeffrey Pfau e577df2142 Fix data format 3 2013-04-09 22:35:38 -07:00
Jeffrey Pfau d3abd2dc63 Minor ROM access optimization 2013-04-09 22:20:35 -07:00
Jeffrey Pfau 027e27caa4 Add data form 3 2013-04-09 04:20:14 -07:00
Jeffrey Pfau 56c3685ba6 ADD/SUB 1 stubs 2013-04-09 03:20:32 -07:00
Jeffrey Pfau 2618c39a5d Macro-insanity for Thumb 2013-04-09 03:15:50 -07:00
Jeffrey Pfau 76dbfce3c3 Start filling in THUMB table with insane preprocessor tricks 2013-04-09 02:57:24 -07:00
Jeffrey Pfau 70eb3634a0 Fix warnings + LDR[B]T/STR[B]T 2013-04-08 03:14:18 -07:00
Jeffrey Pfau 9a1fb100c7 Load/store working RAM 2013-04-08 03:13:37 -07:00
Jeffrey Pfau 93a2f16066 Loading 8/16 bits from ROM 2013-04-08 02:13:40 -07:00
Jeffrey Pfau 67c00f378a Ensure CPSR privilege gets updated in MSR 2013-04-08 00:21:28 -07:00
Jeffrey Pfau 37ad6218da Don't double-execute AL instructions 2013-04-08 00:17:54 -07:00
Jeffrey Pfau 4f3e77c87e Implement MSR 2013-04-08 00:15:16 -07:00
Jeffrey Pfau 4bba75dd0a Separate out ISA files 2013-04-07 21:15:32 -07:00
Jeffrey Pfau b02fdd3dda Remove inline conditions and add ARM specialization 2013-04-07 20:37:48 -07:00
Jeffrey Pfau 186068adfe Start filling in ARMBoard 2013-04-07 13:25:45 -07:00
Jeffrey Pfau 120b85713d Mode switching 2013-04-07 02:36:41 -07:00
Jeffrey Pfau bda71cafc2 ALU instructions can write to PC 2013-04-07 02:01:14 -07:00
Jeffrey Pfau 6e3a9a9508 Fix writing to PC 2013-04-07 01:57:04 -07:00
Jeffrey Pfau 68f2eed84d Mini-test 2013-04-07 01:39:49 -07:00
Jeffrey Pfau 9575e7f0d2 Fix B 2013-04-07 01:39:08 -07:00
Jeffrey Pfau 0e2394e7d5 De-inline ARMStep 2013-04-07 01:46:48 -07:00
Jeffrey Pfau b23f1ee3e3 GBA ROM loading 2013-04-07 01:46:28 -07:00
Jeffrey Pfau 340d3ce6a7 Implement B 2013-04-06 20:16:14 -07:00
Jeffrey Pfau 5c7b4a98c6 Load from ARM table now that we have one 2013-04-06 20:06:51 -07:00
Jeffrey Pfau 6bd7a5ee53 Fill remainder of table 2013-04-06 20:01:32 -07:00
Jeffrey Pfau 7a0fb72e7e Stub out SWI 2013-04-06 19:58:01 -07:00
Jeffrey Pfau d620357ac8 Stub out coprocessor 2013-04-06 19:52:45 -07:00
Jeffrey Pfau 5dd2379dd5 Cleanup 2013-04-06 19:38:14 -07:00
Jeffrey Pfau f2a1257fbb Stub out branch instructions 2013-04-06 19:22:14 -07:00
Jeffrey Pfau 1858dfeb1c Stub out LDM/STM 2013-04-06 18:44:52 -07:00
Jeffrey Pfau 7b82cc0040 Fill in LDR/STR block 2013-04-06 13:05:53 -07:00
Jeffrey Pfau befba57fe6 Simple error checking 2013-04-06 04:34:19 -07:00
Jeffrey Pfau 9efc945f1b Add store callbacks 2013-04-06 04:20:44 -07:00
Jeffrey Pfau 96da9c7ef1 Partially implement LDR/STR and friends 2013-04-06 04:16:34 -07:00
Jeffrey Pfau 92e74a78e1 Apparently I can't count to 8 2013-04-06 02:49:54 -07:00
Jeffrey Pfau cb2469c4f4 Filler for more instructions 2013-04-06 00:32:01 -07:00
Jeffrey Pfau a01fc986a3 Begin GBA structure 2013-04-05 02:17:22 -07:00
Jeffrey Pfau cd07dee7b1 Implement immediate shifter 2013-04-05 00:44:53 -07:00
Jeffrey Pfau c07df4a337 Fill in immediates 2013-04-04 03:12:22 -07:00
Jeffrey Pfau 63f6f53a80 Implement BIC, MOV, MVN, ORR 2013-04-04 02:42:17 -07:00
Jeffrey Pfau dbee1e871e Add stubs, including for illegal instructions 2013-04-04 02:36:53 -07:00
Jeffrey Pfau e093960316 Fill in more opcodes, implement CMN, CMP, TEQ, TST 2013-04-04 02:31:32 -07:00
Jeffrey Pfau fd4ee12eb5 Implement ADD, ADC, RSB, RSC, SUB 2013-04-04 02:04:51 -07:00
Jeffrey Pfau c1a8042db4 Fill in more opcodes, implement EOR 2013-04-04 01:27:51 -07:00
Jeffrey Pfau 4025bf89f2 Add boilerplate for instructions 2013-04-04 00:46:50 -07:00