Jeffrey Pfau
|
82a4fa094b
|
Initialize debugger->lastCommand
|
2013-04-14 03:47:11 -07:00 |
Jeffrey Pfau
|
cd75d3b399
|
Implement LDR[S]B/LDR[S]H (2)
|
2013-04-14 03:38:09 -07:00 |
Jeffrey Pfau
|
9cd468794e
|
Implement BIC
|
2013-04-14 03:31:35 -07:00 |
Jeffrey Pfau
|
288eba1f80
|
Fix POP {pc}
|
2013-04-14 03:28:58 -07:00 |
Jeffrey Pfau
|
3b3b6e0546
|
Implement MVN
|
2013-04-14 03:26:04 -07:00 |
Jeffrey Pfau
|
3121ed0bb6
|
Fix BX
|
2013-04-14 03:23:37 -07:00 |
Jeffrey Pfau
|
8eb8cdfad8
|
Implement SUB(1)
|
2013-04-14 03:15:21 -07:00 |
Jeffrey Pfau
|
18b1fd490f
|
Implement SUB(3)
|
2013-04-14 03:13:06 -07:00 |
Jeffrey Pfau
|
280fc18cff
|
Implement LDRB(1)
|
2013-04-14 03:10:25 -07:00 |
Jeffrey Pfau
|
ee5375a8ff
|
Implement CMP(2)
|
2013-04-14 03:08:07 -07:00 |
Jeffrey Pfau
|
b541b99d0c
|
Implement NEG
|
2013-04-14 03:06:11 -07:00 |
Jeffrey Pfau
|
53212baee5
|
Implement SUB(2)
|
2013-04-14 03:05:12 -07:00 |
Jeffrey Pfau
|
5be88fe123
|
Implement LDRH(1)
|
2013-04-14 03:00:06 -07:00 |
Jeffrey Pfau
|
ce593c4bfa
|
Implement STRB(1)
|
2013-04-14 02:58:05 -07:00 |
Jeffrey Pfau
|
7c8d76eb06
|
Implement BX
|
2013-04-14 02:55:12 -07:00 |
Jeffrey Pfau
|
d7ff6aa14b
|
Add missing field for breakpoints
|
2013-04-14 02:54:58 -07:00 |
Jeffrey Pfau
|
81909bed56
|
Fix indentation of LSR(2)/ASR(2)
|
2013-04-14 02:51:21 -07:00 |
Jeffrey Pfau
|
97ce972b2a
|
Implement LSR(2)
|
2013-04-14 02:49:07 -07:00 |
Jeffrey Pfau
|
76a85c763c
|
Rudimentary breakpoints
|
2013-04-14 02:42:09 -07:00 |
Jeffrey Pfau
|
baad7b50bd
|
Add n command, and command repetition
|
2013-04-13 14:06:57 -07:00 |
Jeffrey Pfau
|
4df2d6de8f
|
Pause on stub opcodes
|
2013-04-13 13:56:29 -07:00 |
Jeffrey Pfau
|
e5379c99e0
|
Add ability to run code indefinitely (or at least until we crash)
|
2013-04-13 13:50:41 -07:00 |
Jeffrey Pfau
|
dbe9796b34
|
Implement B
|
2013-04-13 12:38:47 -07:00 |
Jeffrey Pfau
|
abd522a2ce
|
Implement ADD(4)
|
2013-04-13 12:32:15 -07:00 |
Jeffrey Pfau
|
bc4924cef5
|
Implement CMP(3)
|
2013-04-13 12:28:24 -07:00 |
Jeffrey Pfau
|
aa14ed441c
|
Implement AND, EOR and ORR
|
2013-04-13 01:50:21 -07:00 |
Jeffrey Pfau
|
75fdcd6750
|
Add missing CPSR update for ASR(2)
|
2013-04-13 01:48:00 -07:00 |
Jeffrey Pfau
|
c51ad65cac
|
Implement ASR(2)
|
2013-04-13 01:42:34 -07:00 |
Jeffrey Pfau
|
5094b7717a
|
Add memory reading commands to debugger
|
2013-04-13 01:36:01 -07:00 |
Jeffrey Pfau
|
5465543acc
|
Properly recognize syntax errors
|
2013-04-13 01:27:05 -07:00 |
Jeffrey Pfau
|
0180ee090e
|
Print hex
|
2013-04-13 01:25:21 -07:00 |
Jeffrey Pfau
|
f715534083
|
Begin command line parsing
|
2013-04-13 01:23:41 -07:00 |
Jeffrey Pfau
|
10884de57a
|
Add ability to print current instruction
|
2013-04-13 00:22:27 -07:00 |
Jeffrey Pfau
|
67750e351b
|
Fix sign-extension on BL1
|
2013-04-12 22:59:19 -07:00 |
Jeffrey Pfau
|
eed0e77079
|
Implement B(1)
|
2013-04-12 22:58:50 -07:00 |
Jeffrey Pfau
|
be8849d7fe
|
Implement CMP(1)
|
2013-04-12 22:44:51 -07:00 |
Jeffrey Pfau
|
3a097dca96
|
Implement ADD(3), refactor other ADDs
|
2013-04-12 22:34:44 -07:00 |
Jeffrey Pfau
|
36670b3fa2
|
Implement LSR(1) and reindent LSL(1)
|
2013-04-12 22:24:35 -07:00 |
Jeffrey Pfau
|
9ca65038ed
|
Implement LDR(4)
|
2013-04-12 22:18:46 -07:00 |
Jeffrey Pfau
|
9f77c32375
|
Implement ADD(1)
|
2013-04-12 22:17:37 -07:00 |
Jeffrey Pfau
|
d7ddbee448
|
Fix BL(1)
|
2013-04-12 22:14:01 -07:00 |
Jeffrey Pfau
|
f86fb9dc74
|
Implement LDR(1)
|
2013-04-12 22:06:17 -07:00 |
Jeffrey Pfau
|
33fc9587cc
|
Implement STR(1)
|
2013-04-12 21:57:50 -07:00 |
Jeffrey Pfau
|
c8f85a657e
|
Implement STR(3)
|
2013-04-12 21:48:30 -07:00 |
Jeffrey Pfau
|
3e57e46046
|
Implement ADD(2)
|
2013-04-12 21:48:19 -07:00 |
Jeffrey Pfau
|
b5182915d7
|
Command to break into attached debugger
|
2013-04-12 21:27:43 -07:00 |
Jeffrey Pfau
|
a7bc99c846
|
Implement LDR(3)
|
2013-04-12 20:09:27 -07:00 |
Jeffrey Pfau
|
57f2cccacf
|
Implement STRH(1)
|
2013-04-12 20:06:58 -07:00 |
Jeffrey Pfau
|
21ee7946f1
|
Implement LSL(1)
|
2013-04-12 20:00:14 -07:00 |
Jeffrey Pfau
|
71c68fe79f
|
Implement ADD(6)
|
2013-04-12 19:59:55 -07:00 |
Jeffrey Pfau
|
21df1c48c2
|
Implement MOV(1)
|
2013-04-12 02:44:04 -07:00 |
Jeffrey Pfau
|
9ab3b0c20a
|
Implement ADD(7)/SUB(4)
|
2013-04-12 02:22:37 -07:00 |
Jeffrey Pfau
|
1ac7f0eb15
|
Implement MOV(3)
|
2013-04-12 02:15:47 -07:00 |
Jeffrey Pfau
|
37ce1383fc
|
Set bits in MSR properly
|
2013-04-12 02:10:09 -07:00 |
Jeffrey Pfau
|
6097890251
|
Print proper register
|
2013-04-12 02:04:51 -07:00 |
Jeffrey Pfau
|
688af6cdee
|
Add some basic input to the debugger
|
2013-04-12 02:03:11 -07:00 |
Jeffrey Pfau
|
1db7f5b179
|
Initial debugger
|
2013-04-12 01:32:43 -07:00 |
Jeffrey Pfau
|
b07e052698
|
Move CMakeList
|
2013-04-11 23:58:13 -07:00 |
Jeffrey Pfau
|
d90d7d1899
|
Implement BL
|
2013-04-11 03:14:09 -07:00 |
Jeffrey Pfau
|
133d574667
|
Implement LDMIA/STMIA/PUSH/POP
|
2013-04-11 03:01:07 -07:00 |
Jeffrey Pfau
|
1616ec83a2
|
Stub out incomplete addressing mode 1 opcodes
|
2013-04-11 02:13:35 -07:00 |
Jeffrey Pfau
|
4fbed66bdb
|
Start fleshing out addressing mode 1
|
2013-04-11 01:32:30 -07:00 |
Jeffrey Pfau
|
d278429b43
|
Implement BX
|
2013-04-11 00:14:12 -07:00 |
Jeffrey Pfau
|
a511df7920
|
Put stub definitions in all of Thumb
|
2013-04-10 23:38:18 -07:00 |
Jeffrey Pfau
|
7e5de27f43
|
Add ability to run Thumb code
|
2013-04-10 23:34:50 -07:00 |
Jeffrey Pfau
|
9a0d14645b
|
Log stubs
|
2013-04-10 22:52:46 -07:00 |
Jeffrey Pfau
|
9a7f0f4a74
|
Stub out BL, finishing Thumb table
|
2013-04-10 21:11:05 -07:00 |
Jeffrey Pfau
|
87863ad97a
|
Stub out B
|
2013-04-10 21:09:22 -07:00 |
Jeffrey Pfau
|
cbc17ad77e
|
Stub out SWI
|
2013-04-10 21:05:19 -07:00 |
Jeffrey Pfau
|
e89f49459a
|
Stub out conditional branches
|
2013-04-10 21:04:41 -07:00 |
Jeffrey Pfau
|
d5adcac319
|
Stub out LDMIA/STMIA
|
2013-04-10 20:58:05 -07:00 |
Jeffrey Pfau
|
0db11ec6bb
|
Stub out BKPT (not in ARMv4T, but still useful)
|
2013-04-10 20:50:56 -07:00 |
Jeffrey Pfau
|
5e78400a25
|
Stub out POP/PUSH
|
2013-04-10 00:00:24 -07:00 |
Jeffrey Pfau
|
99d0b76f3b
|
Stub out ADD7 and SUB4
|
2013-04-09 23:47:37 -07:00 |
Jeffrey Pfau
|
08065d865d
|
Stub out ADD from PC and SP
|
2013-04-09 23:45:08 -07:00 |
Jeffrey Pfau
|
28ecc97671
|
Stub out LDR/STR from SP
|
2013-04-09 23:37:28 -07:00 |
Jeffrey Pfau
|
e3818cf7b6
|
Stub out more load/stores with immediates
|
2013-04-09 23:34:25 -07:00 |
Jeffrey Pfau
|
39c776eb37
|
Stub out more load/store format 2
|
2013-04-09 23:27:37 -07:00 |
Jeffrey Pfau
|
5165e0131e
|
Put in missing BX
|
2013-04-09 23:16:30 -07:00 |
Jeffrey Pfau
|
f42c8d111e
|
Stub out STR2
|
2013-04-09 23:00:31 -07:00 |
Jeffrey Pfau
|
11de611fd2
|
Stub out LDR3
|
2013-04-09 22:57:24 -07:00 |
Jeffrey Pfau
|
5e18eabd04
|
Stub out format 8
|
2013-04-09 22:51:21 -07:00 |
Jeffrey Pfau
|
be021605bc
|
Define data format 5
|
2013-04-09 22:35:51 -07:00 |
Jeffrey Pfau
|
e577df2142
|
Fix data format 3
|
2013-04-09 22:35:38 -07:00 |
Jeffrey Pfau
|
d3abd2dc63
|
Minor ROM access optimization
|
2013-04-09 22:20:35 -07:00 |
Jeffrey Pfau
|
027e27caa4
|
Add data form 3
|
2013-04-09 04:20:14 -07:00 |
Jeffrey Pfau
|
56c3685ba6
|
ADD/SUB 1 stubs
|
2013-04-09 03:20:32 -07:00 |
Jeffrey Pfau
|
2618c39a5d
|
Macro-insanity for Thumb
|
2013-04-09 03:15:50 -07:00 |
Jeffrey Pfau
|
76dbfce3c3
|
Start filling in THUMB table with insane preprocessor tricks
|
2013-04-09 02:57:24 -07:00 |
Jeffrey Pfau
|
70eb3634a0
|
Fix warnings + LDR[B]T/STR[B]T
|
2013-04-08 03:14:18 -07:00 |
Jeffrey Pfau
|
9a1fb100c7
|
Load/store working RAM
|
2013-04-08 03:13:37 -07:00 |
Jeffrey Pfau
|
93a2f16066
|
Loading 8/16 bits from ROM
|
2013-04-08 02:13:40 -07:00 |
Jeffrey Pfau
|
67c00f378a
|
Ensure CPSR privilege gets updated in MSR
|
2013-04-08 00:21:28 -07:00 |
Jeffrey Pfau
|
37ad6218da
|
Don't double-execute AL instructions
|
2013-04-08 00:17:54 -07:00 |
Jeffrey Pfau
|
4f3e77c87e
|
Implement MSR
|
2013-04-08 00:15:16 -07:00 |
Jeffrey Pfau
|
4bba75dd0a
|
Separate out ISA files
|
2013-04-07 21:15:32 -07:00 |
Jeffrey Pfau
|
b02fdd3dda
|
Remove inline conditions and add ARM specialization
|
2013-04-07 20:37:48 -07:00 |
Jeffrey Pfau
|
186068adfe
|
Start filling in ARMBoard
|
2013-04-07 13:25:45 -07:00 |
Jeffrey Pfau
|
120b85713d
|
Mode switching
|
2013-04-07 02:36:41 -07:00 |
Jeffrey Pfau
|
bda71cafc2
|
ALU instructions can write to PC
|
2013-04-07 02:01:14 -07:00 |
Jeffrey Pfau
|
6e3a9a9508
|
Fix writing to PC
|
2013-04-07 01:57:04 -07:00 |
Jeffrey Pfau
|
68f2eed84d
|
Mini-test
|
2013-04-07 01:39:49 -07:00 |
Jeffrey Pfau
|
9575e7f0d2
|
Fix B
|
2013-04-07 01:39:08 -07:00 |
Jeffrey Pfau
|
0e2394e7d5
|
De-inline ARMStep
|
2013-04-07 01:46:48 -07:00 |
Jeffrey Pfau
|
b23f1ee3e3
|
GBA ROM loading
|
2013-04-07 01:46:28 -07:00 |
Jeffrey Pfau
|
340d3ce6a7
|
Implement B
|
2013-04-06 20:16:14 -07:00 |
Jeffrey Pfau
|
5c7b4a98c6
|
Load from ARM table now that we have one
|
2013-04-06 20:06:51 -07:00 |
Jeffrey Pfau
|
6bd7a5ee53
|
Fill remainder of table
|
2013-04-06 20:01:32 -07:00 |
Jeffrey Pfau
|
7a0fb72e7e
|
Stub out SWI
|
2013-04-06 19:58:01 -07:00 |
Jeffrey Pfau
|
d620357ac8
|
Stub out coprocessor
|
2013-04-06 19:52:45 -07:00 |
Jeffrey Pfau
|
5dd2379dd5
|
Cleanup
|
2013-04-06 19:38:14 -07:00 |
Jeffrey Pfau
|
f2a1257fbb
|
Stub out branch instructions
|
2013-04-06 19:22:14 -07:00 |
Jeffrey Pfau
|
1858dfeb1c
|
Stub out LDM/STM
|
2013-04-06 18:44:52 -07:00 |
Jeffrey Pfau
|
7b82cc0040
|
Fill in LDR/STR block
|
2013-04-06 13:05:53 -07:00 |
Jeffrey Pfau
|
befba57fe6
|
Simple error checking
|
2013-04-06 04:34:19 -07:00 |
Jeffrey Pfau
|
9efc945f1b
|
Add store callbacks
|
2013-04-06 04:20:44 -07:00 |
Jeffrey Pfau
|
96da9c7ef1
|
Partially implement LDR/STR and friends
|
2013-04-06 04:16:34 -07:00 |
Jeffrey Pfau
|
92e74a78e1
|
Apparently I can't count to 8
|
2013-04-06 02:49:54 -07:00 |
Jeffrey Pfau
|
cb2469c4f4
|
Filler for more instructions
|
2013-04-06 00:32:01 -07:00 |
Jeffrey Pfau
|
a01fc986a3
|
Begin GBA structure
|
2013-04-05 02:17:22 -07:00 |
Jeffrey Pfau
|
cd07dee7b1
|
Implement immediate shifter
|
2013-04-05 00:44:53 -07:00 |
Jeffrey Pfau
|
c07df4a337
|
Fill in immediates
|
2013-04-04 03:12:22 -07:00 |
Jeffrey Pfau
|
63f6f53a80
|
Implement BIC, MOV, MVN, ORR
|
2013-04-04 02:42:17 -07:00 |
Jeffrey Pfau
|
dbee1e871e
|
Add stubs, including for illegal instructions
|
2013-04-04 02:36:53 -07:00 |
Jeffrey Pfau
|
e093960316
|
Fill in more opcodes, implement CMN, CMP, TEQ, TST
|
2013-04-04 02:31:32 -07:00 |
Jeffrey Pfau
|
fd4ee12eb5
|
Implement ADD, ADC, RSB, RSC, SUB
|
2013-04-04 02:04:51 -07:00 |
Jeffrey Pfau
|
c1a8042db4
|
Fill in more opcodes, implement EOR
|
2013-04-04 01:27:51 -07:00 |
Jeffrey Pfau
|
4025bf89f2
|
Add boilerplate for instructions
|
2013-04-04 00:46:50 -07:00 |
Jeffrey Pfau
|
bf72532715
|
Add more framework for loading instructions
|
2013-04-03 22:34:49 -07:00 |
Jeffrey Pfau
|
009bef870c
|
Initial commit
|
2013-04-03 22:12:15 -07:00 |