Commit Graph

2850 Commits

Author SHA1 Message Date
Jaklyy 7590c48471 Revert "revert arm9 main ram dma again (again (again))"
This reverts commit c90f10d056.
2024-12-16 11:45:14 -05:00
Jaklyy 67198a72bd why did i remove that
This reverts commit 45be951a0f.
2024-12-16 10:32:33 -05:00
Jaklyy 5c5f4364db run arm 7 first?
it's faster...?
2024-12-16 10:20:10 -05:00
Jaklyy c90f10d056 revert arm9 main ram dma again (again (again)) 2024-12-16 10:19:51 -05:00
Jaklyy 29421f1d27 re-enable mainram dma
it's not bugged, it's also not inaccurate.
something else is the issue...
2024-12-16 09:23:54 -05:00
Jaklyy e77c2011bc slightly optimize main loop 2024-12-15 22:02:41 -05:00
Jaklyy c40efab62f revert main ram dma
broke stuff
2024-12-15 22:01:44 -05:00
Jaklyy c96b49e9cd Revert "improve(?) irq handling"
This reverts commit 443ecb313d.
2024-12-15 21:48:27 -05:00
Jaklyy 93242e1189 revert most scheduler changes 2024-12-15 21:48:22 -05:00
Jaklyy 443ecb313d improve(?) irq handling
...i dont think this fixes anything
2024-12-15 20:51:13 -05:00
Jaklyy 45be951a0f this should be smarter 2024-12-15 18:48:35 -05:00
Jaklyy db1991276a tweak scheduling to be a little less gross 2024-12-15 18:40:21 -05:00
Jaklyy 5b07765eb5 misc tweaks to dma 2024-12-15 10:42:52 -05:00
Jaklyy 2247f17f4f implement a main ram burst restart behavior 2024-12-15 06:34:36 -05:00
Jaklyy d912429d8c comment out some replaced stuff 2024-12-14 23:36:28 -05:00
Jaklyy c902dcfc98 improve main ram dma timings 2024-12-14 23:23:00 -05:00
Jaklyy 2051d412d1 implement MR cont. for arm7 dma; also a hack?
the hack is to make arm9 dma contention work with prior improvements to synchronization
2024-12-14 17:17:44 -05:00
Jaklyy 4ea0e60e18 minor fix(?)
this should fix something?
2024-12-14 13:32:54 -05:00
Jaklyy 5e945669f5 hopefully reduce desync potential a little? 2024-12-14 10:45:08 -05:00
Jaklyy 610ac2491a disable main ram contention for arm9 dma
caused innumerable issues
will need a more comprehensive rewrite later
2024-12-14 09:38:02 -05:00
Jaklyy ac1d790d7e fix the system timestamp being run wayyyy too fast
oh no that was covering up SO many bugs hhhhsdfghhg
2024-12-14 00:15:17 -05:00
Jaklyy a445c0d32c this makes a bit more sense 2024-12-13 22:08:34 -05:00
Jaklyy cce5070077 probably not any faster 2024-12-13 21:32:15 -05:00
Jaklyy 456d07da03 unbork gxfifo stalls 2024-12-13 15:35:44 -05:00
Jaklyy 642f085975 probably unborks gxfifo stalls 2024-12-13 13:15:38 -05:00
Jaklyy 73be2f3e01 tweak dmas to be more accurate (actually less?) 2024-12-13 13:09:42 -05:00
Jaklyy d341260e5a dma rewrite 1 2024-12-10 21:23:02 -05:00
Jaklyy feb1cd562d clarify some more write buffer details 2024-12-10 12:04:43 -05:00
Jaklyy 96c8f67d5f implement bit 10 of exmemcnt 2024-12-10 08:04:00 -05:00
Jaklyy b048e0cbfd improve ExMemCnt handling and defaults 2024-12-09 19:30:47 -05:00
Jaklyy 8382769073 fix a main loop freeze; exmemcnt bit 15 starts set
fixes twilight menu
2024-12-09 15:52:50 -05:00
Jaklyy 52e14612b1 probably faster to directly access main ram? 2024-12-09 12:25:23 -05:00
Jaklyy 0111ee7fac micro-optimization 2024-12-09 11:11:24 -05:00
Jaklyy 918df047b8 cache line boundary align condition lut table 2024-12-09 10:03:47 -05:00
Jaklyy cbdd6a0faf cacheline align register array
IM SORRY GENERIC
2024-12-09 09:10:24 -05:00
Jaklyy fe9a9ee27d actually those do literally nothing 2024-12-09 00:39:24 -05:00
Jaklyy 33f6218972 avoid checking T bit every instruction 2024-12-09 00:31:21 -05:00
Jaklyy aa2cdc37a1 optimize one of the main loops 2024-12-08 23:10:53 -05:00
Jaklyy f823a92020 fix branches being able to break the queue system
fixes bw2
2024-12-08 22:41:32 -05:00
Jaklyy 7a4234dcd8 fix writeback when rn is also rd in ldr
something *has* to rely on this, as stupid as it seems
2024-12-08 19:49:08 -05:00
Jaklyy 1a1934df00 ...removing the (s32) fixes sign extension? ig??? 2024-12-08 19:24:19 -05:00
Jaklyy 0df4369305 tweak scheduler for better performance
might be less accurate
2024-12-08 15:25:18 -05:00
Jaklyy 91752c1925 fix emulator hanging under certain circumstances 2024-12-08 14:24:33 -05:00
Jaklyy 8e6755ce2c jakly pls 2024-12-08 11:20:36 -05:00
Jaklyy bda05a756e only recalc mpu lut if it changed 2024-12-08 11:19:49 -05:00
Jaklyy 8209fdebb4 fix main ram timestamp
i hate order of operations
2024-12-08 10:02:25 -05:00
Jaklyy e69a2aa1b5 write buffer shouldn't continue resolving main ram accesses if it passes the a7 ts 2024-12-08 09:05:33 -05:00
Jaklyy 68b4d96f0d Queue ICache Prefetch 2024-12-08 00:25:44 -05:00
Jaklyy b40c6bc41d implement write buffer 2024-12-08 00:19:43 -05:00
Jaklyy d14c5ea246 re-add itcm delay for ldm/stm 2024-12-07 10:07:57 -05:00