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154 Commits

Author SHA1 Message Date
MerryMage be6aec9932 Arm64Emitter: Add BFXIL 2021-01-31 12:04:57 +00:00
JosJuice 2d9ea42df2 Arm64Emitter: Add asserts for LDP/STP imm out of range 2021-01-30 00:25:33 +01:00
Dentomologist e3237661ec Arm64Emitter: Convert ShiftType to enum class 2021-01-17 16:21:38 -08:00
Dentomologist 70c54065ab Arm64Emitter: Convert IndexType to enum class 2021-01-15 23:27:11 -08:00
Lioncash 95cc53edec Arm64Emitter: Convert ArithOption enums into enum classes 
Makes the enums strongly typed. While we're at it, we can also make
these enums private.
 2021-01-01 07:10:41 -05:00
Lioncash cca0dffebd Arm64Emitter: Add shorthand member functions for hint instructions 
Allows for more concise code.
 2020-12-30 20:49:20 -05:00
Lioncash 6046a15267 Arm64Emitter: Make ShiftAmount enum an enum class 
Reduces namespace pollution and makes the enum strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash fab2053439 Arm64Emitter: Make RoundingMode enum an enum class 
Prevents namespace pollution and makes the enum members strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash d87ec71615 Arm64Emitter: Make PStateField enum an enum class 
Prevents namespace pollution and makes the enum members strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash 5c3f2fde22 Arm64Emitter: Make BarrierType enum an enum class 
Prevents namespace pollution and enforces strong typing.
 2020-12-30 20:49:20 -05:00
Lioncash f21c740919 Arm64Emitter: Make SystemHint enum an enum class 
Avoids polluting the namespace and makes the members strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash 5011c155ec Arm64Emitter: Make type member of FixupBranch an enum class 
Eliminates some magic numbers and makes the type member strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash 2fa4729815 Arm64Emitter: Annotate switch fallthrough 
Silences warnings and makes intent explicit.
 2020-12-30 20:49:20 -05:00
Lioncash d780ad1102 Arm64Emitter: Make use of std::optional 
Allows eliminating some out variables in favor of optional, which allows
narrowing visible scope of variables.
 2020-12-30 20:49:16 -05:00
MerryMage d695fcb126 BitUtils: Add CountLeadingZeros 2020-12-27 22:56:43 +00:00
Lioncash 4e8df93f41 Common: Migrate logging to fmt 
Continues the migration of our code over to the fmt logger.
 2020-10-23 14:58:03 -04:00
Admiral H. Curtiss 5b52b3e9cb x64Emitter: Check end of allocated space when emitting code. 2020-08-24 19:31:32 +02:00
spycrab 213a9adcff CMake: Fix building ARM64 on Windows 2020-02-12 12:29:31 +01:00
Stenzek d744c5a148 Compile fixes for Windows-on-ARM64 2019-12-28 19:20:41 +10:00
Marshall Mohror 0334dde2cf
Fix typo in comment 2019-11-11 13:20:04 -06:00
Techjar ff972e3673 Reformat repo to clang-format 7.0 rules 2019-05-06 18:48:04 +00:00
MerryMage 9753f21cc7 Arm64Emitter: Remove unsequenced expressions 
Incrementing `it` twice between sequence points is undefined behavior.
 2018-08-30 07:38:37 +01:00
Lioncash 208be26bb4 Arm64Emitter: Make the Align* functions return a non-const data pointer 
Similar in nature to e28d063539 in which
this same change was applied to the x64 emitter.

There's no real requirement to make this const, and this should also
be decided by the calling code, considering we had places that would
simply cast away the const and carry on
 2018-08-27 09:44:38 -04:00
Lioncash 67b015d76b Arm64Emitter: Get rid of a pointer cast within SetJumpTarget() 
Type punning like this is undefined behavior. Instead, we use std::memcpy to
copy the necessary data over, which is well defined (as it treats both
the source and destination as unsigned char).
 2018-08-14 23:47:53 -04:00
Lioncash 6fd7a79b93 Arm64Emitter: Use Common::BitCast where applicable 
Gets rid of the need to set up memcpy boilerplate to reinterpret between
floating-point and integers.

While we're at it, also do a minor bit of tidying.
 2018-05-29 18:19:01 -04:00
spycrab 40bb9974f2 Reformat all the things! 2018-04-12 21:28:39 +02:00
Lioncash f889cae8c4
Arm64Emitter: Satisfy unrelated linter issues that cropped up by modifying the cpp file 2018-03-23 19:17:44 -04:00
Lioncash 91cefe6c8a
Arm64Emitter: Make IsImmArithmetic, IsImmLogical, FPImm8ToFloat, and FPImm8FromFloat internally linked 
These aren't used anywhere outside of the emitter. Centralizes them under an anonymous namespace.
 2018-03-23 19:17:26 -04:00
Lioncash b11c237c43
Arm64Emitter: Remove unnecessary V8_UINT64_C preprocessor macro 
UINT64_C is provided via <cstdint>, so we can just use that instead.
 2018-03-23 13:31:48 -04:00
Lioncash 03671a5534
Arm64Emitter: Remove duplicate IsPowerOf2 function 
We can just use the generified version in MathUtil.
 2018-03-23 13:31:44 -04:00
Lioncash 7926a0c814 Use __func__ instead of __FUNCTION__ where applicable 
This replaces usages of the non-standard __FUNCTION__ macro with the standard
mandated __func__ identifier.

__FUNCTION__ is a preprocessor definition that is provided as an
extension by compilers. This was the only convenient option to rely on
pre-C++11. However, C++11 and greater mandate the predefined identifier
__func__, which lets us accomplish the same thing.

The difference between the two, however, is that __func__ isn't a
preprocessor macro, it's an actual identifier that exists at function
scope. The C++17 draft standard (N4659) at section [dcl.fct.def.general]
paragraph 8 states:

"
The function-local predefined variable __func__ is defined as if a
definition of the form

static const char __func__[] = "function-name ";

had been provided, where function-name is an implementation-defined
string. It is unspecified whether such
a variable has an address distinct from that of any other object in the
program.
"

Thankfully, we don't do any macro or string concatenation with __FUNCTION__
that can't be modified to use __func__.
 2018-03-16 13:41:53 -04:00
Lioncash 75f5fcdfee Assert: Remove unused parameter from DEBUG_ASSERT 
This brings the macro in line with the regular ASSERT macro, which only has one
macro parameter.
 2018-03-16 13:01:11 -04:00
Lioncash 50a476c371 Assert: Uppercase assertion macros 
Macros should be all upper-cased. This is also kind of a wart that's
been sticking out for quite a while now (we avoid prefixing
underscores).
 2018-03-14 22:03:12 -04:00
Jonathan Hamilton 8ae76a6680 Fix arm64 MOVI2R for addresses between 2gb and 4gb offset from PC 
The PC offset ADRP() path takes a s32 value, but the input offset was
being tested as abs(ptr) < 0xFFFFFFFF. This caused values between
0x80000000 and 0xFFFFFFFF to incorrectly use this path, despite the
offsets not being representable in an s32.

This caused a crash in the VertexLoader on android 8.1 immediate in wind
waker (and possibly all other apps on android 8.1) as the jit and data
sections happened to be loaded 4gb apart in virtual memory, causing some
pointers to hit this
 2017-12-09 13:21:58 -08:00
degasus 304e601ad3 JitArm64: Reimplement aarch64 cycle counters. 
CNTVCT_EL0 is force-enabled on all linux plattforms.
Windows is untested, but as this is the best way to get *any* low
overhead performance counters, they likely use it as well.
 2017-09-02 13:24:37 +02:00
degasus b00c60618b JitArm64: Fix rlwinmx. 
Seems like I was wrong that ANDI2R doesn't require a temporary register here.
There is *one* case when the mask won't fit in the ARM AND instruction:
mask = 0xFFFFFFFF
But let's just use MOV instead of AND here for this case...
 2017-08-22 08:47:43 +02:00
Markus Wick d78009877b JitArm64: Fix LSL/LSR/ROR/ASR wrappers. 
The other method has a latency of 2 cycles. This also improves the
throughput a lot.
 2017-08-12 00:00:41 +02:00
Tillmann Karras c54c49714d Arm64Emitter: add FRECPE 2017-05-03 08:02:35 +01:00
Michael Maltese 3d7bace9da Arm64Emitter: extract lambda to AddImmediate() 
Fixes warning:

```
Source/Core/Common/Arm64Emitter.cpp:4108:31: error: declaration shadows a local variable [-Werror,-Wshadow]
    auto addi = [this](ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags) {
                                ^
  /var/lib/buildbot/slave/pr-android/build/Source/Core/Common/Arm64Emitter.cpp:4105:46: note: previous declaration is here
  void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags,
                                               ^
```
 2017-03-25 14:21:19 -07:00
Michael Maltese c58ba93503 Arm64: Use PRIi64/PRIx64 for printf 2017-03-25 14:20:44 -07:00
degasus 6aa54a029e JitArm64: Optimize GPR register push/pop. 2017-02-11 00:59:12 +01:00
BhaaL 23d99f2f2c specify custom brace style to fix unions 
BreakBeforeBraces: Allman apparently includes all styles,
except for AfterUnion (which is false) when using clang-format -dump-config
 2017-01-05 12:55:13 +01:00
Léo Lam 31ccfffd38 Common: Add alignment header 
Gets rid of duplicated alignment code.
 2016-12-06 20:33:53 +01:00
degasus 8ad98d0046 ArmEmitter: Merge AddI2R helpers. 2016-10-27 19:19:06 +02:00
degasus 694e9b4132 JitArm64: ADDI2R optimizations 2. 2016-10-27 19:19:06 +02:00
degasus 1df694626d JitArm64: Optimize addi2r & subi2r. 2016-10-26 21:54:13 +02:00
degasus df250b84cc JitArm64: Avoid MOVI2R is possible. 
Just use all kind of ADDI2R, SUBI2R, ...
They have some optimizations internally.
 2016-10-26 21:54:09 +02:00
degasus 7c9bba2213 Arm64Emitter: Fix std::array initializer. 2016-09-26 22:17:25 +02:00
Bernhard Urban 976da3707a arm64: add comment about data cache flushing 2016-09-10 08:05:16 +02:00
Bernhard Urban fff8221b63 arm64: fixes around icache flushing 2016-09-10 02:31:07 +02:00
Pierre Bourdon 3570c7f03a Reformat all the things. Have fun with merge conflicts. 2016-06-24 10:43:46 +02:00
degasus 9ed465f4ac JitArm64: Implement mulhwx 2016-03-04 22:51:46 +01:00
mathieui f15ffda5a7 Correct ampersands as well 2016-01-21 21:27:56 +01:00
mathieui 3e283ea9f1 More asterisks 2016-01-21 21:16:51 +01:00
mathieui 78aa398e7c Common: asterisks go against the type name 
not the variable name
 2016-01-21 20:46:25 +01:00
Lioncash 2630752ffe Arm64Emitter: Get rid of a pointer cast 2015-10-22 15:32:11 -04:00
Lioncash 018c85c248 Arm64Emitter: Mark trivial functions as constexpr 2015-10-22 15:22:38 -04:00
Lioncash 19ac565e0d Common: Move asserts to their own header 2015-09-26 18:51:27 -04:00
Ryan Houdek 2ad26ab3e9 [AArch64] Fix Test&Branch to relative location instructions. 
Wasn't masking by the size of the offset encoding so negative values were killing the instruction
Missed commiting this in my integer gatherpipe PR.
Fixes crashing on AArch64.
 2015-09-07 13:38:58 -05:00
Ryan Houdek d003934b8a Merge pull request #2929 from Sonicadvance1/aarch64_optimize_gpr_flush 
Aarch64 optimize gpr flush
 2015-08-31 10:55:45 -05:00
Ryan Houdek f2c17436ab [AArch64] Fix issue in emitter. 
Loadstore pairs support only signed offsets, not unsigned.
 2015-08-30 23:05:59 -05:00
Ryan Houdek b907576510 [AArch64] Support profiling by cycle counters if they are available to EL0 2015-08-30 10:25:16 -05:00
Ryan Houdek 4fa23abbe1 [AArch64] Implement MOVI and ORR(imm) in the NEON emitter. 2015-08-23 15:34:53 -05:00
degasus 9bfff0d461 JitArm64: Fix jit clearing 
We have to reset m_lastCacheFlushEnd on clearing.
 2015-08-15 11:41:01 +02:00
Lioncash 144ea9f4aa Arm64Emitter: Fix encoding of '2-reg misc' variant of FCMEQ 2015-08-10 19:48:36 -04:00
Ryan Houdek 922d476dab [AArch64] Fix FCMGE instruction encoding. 
Fixes a crash when ps_sel is used (PSO 1&2 intro movies).
 2015-08-09 14:54:55 -05:00
degasus b8dd68beef JitArm64: Far Code Cache 2015-07-12 09:41:32 +02:00
Lioncash d09d59007a Arm64Emitter: Add a missing const specifier for an array table 2015-07-02 11:09:44 -04:00
Ryan Houdek afc3d30f5c [AArch64] Implement BFI & UBFIZ in the emitter. 
Also fixes a bug in the UBFX instruction emitter. Naughty Naughty PPSSPP, not testing emitter functions you add.
 2015-06-29 19:00:22 -05:00
Ryan Houdek 5dc148159f [AArch64] Implement {U, S}QXTN{,2} 
Also split out XTN to XTN and XTN2.
 2015-06-13 23:16:17 -05:00
Lioncash 74b359e390 Arm64Emitter: Remove unused variable from EncodeLoadStoreRegisterOffset 2015-06-13 14:27:15 -04:00
Ryan Houdek 3d2b116323 [AArch64] Implement a couple instructions in the emitter. 
Implements LD2R.
Implements LD1R/LD2R with post-indexing support.
Implements vector min/max instructions.
 2015-06-09 18:10:56 -05:00
Ryan Houdek 8ae12d8005 [AArch64] Add ASIMD LDR/STR with register offset 2015-06-07 19:53:05 -05:00
Ryan Houdek 05b72c5d31 [AArch64] Upstream PPSSPP's emitter changes. 
Requires a minor change to in the JIT to make sure everything still works.
 2015-06-07 19:50:21 -05:00
Tillmann Karras 30ebb2459e Set copyright year to when a file was created 2015-05-25 13:22:31 +02:00
Tillmann Karras cefcb0ace9 Update license headers to GPLv2+ 2015-05-25 13:22:31 +02:00
Ryan Houdek f6511c3ba5 [AArch64] Add an assert to SMOV in the emitter. 
SMOV doesn't have an encoding for moving a 32bit element to a 32bit GPR.
One should use UMOV if they want that.
 2015-03-08 12:29:45 -05:00
Ryan Houdek fbdee7b15f [AArch64] Handle FPR island registers in a less dumb way. 2015-03-03 00:30:05 -06:00
Ryan Houdek f1a9db9bdc [AArch64] Stop violating the AAPCS64 so much. 2015-03-02 11:21:15 -06:00
Ryan Houdek fad46729b0 [AArch64] Implemented paired pushing/popping for the VFP. 
A bit more efficient if we are only pushing two VFP registers.
We can probably be a bit more efficient in the future by mixing paired loadstores in to the other paths as well.
 2015-03-02 06:27:47 -06:00
Ryan Houdek 39e357d62d [AArch64] Implement VFP loadstore paired in the emitter. 2015-03-02 06:27:17 -06:00
Ryan Houdek 8b8310d28c [AArch64] Optimize FPR pushing and popping. 
Previously on FPR pushing and popping we would do a single STR/LDR per quad FPR we wanted to push/pop.
In most of our cases when we are pushing and popping VFP registers they will be consecutive registers that will save more efficiently using the NEON
loadstores that can do up to four quad registers.
So this can potentially cutting instructions down to ~1/4th the amount of instructions if the registers are all consecutive.

On the Cortex-A57 this is basically just an icache improvement, but on the Nvidia Denver this may be optimized to be more efficient. Either way it's a
win.
 2015-03-02 06:27:13 -06:00
Ryan Houdek 120df4c688 [AArch64] Implement loadstore unscaled. 2015-02-16 22:00:43 -06:00
Ryan Houdek 814aaaf538 [AArch64] Implement a couple of emitter instructions. 
These will be used with the vertex loader JIT recompiler.
 2015-02-13 12:16:06 -06:00
Ryan Houdek 20dae1f210 [AArch64] Fix a bunch of emitter asserts. 
Since I've added the msg handler. I found all these asserts that were backwards. So they were asserting on the correct arguments.
 2015-02-13 12:16:05 -06:00
Ryan Houdek c340a324bc Merge pull request #1947 from Sonicadvance1/AArch64_tu_tl_merge 
[AArch64] Implement TU/TL merging.
 2015-01-25 23:07:32 -06:00
Ryan Houdek f24c466e7e [AArch64] Fix AArch64 instruction encoding. 2015-01-25 17:26:18 -06:00
Ryan Houdek 6470227a39 [AArch64] Minor fix in the UMULH/SMULH. 
These two instructions ignore the register encoded in to RA.
 2015-01-22 18:08:49 -06:00
Ryan Houdek 217c2c9d6a [AArch64] Add some more scalar VFP ops to the emitter. 2015-01-20 16:34:32 -06:00
Ryan Houdek 8d5947efac [AArch64] Emitter improvements. 
Adds a bunch of new instructions to the emitter.
 2015-01-18 16:25:40 -06:00
Ryan Houdek c511ee763a [AArch64] Add the float emitter. 2015-01-08 19:55:31 -06:00
Ryan Houdek 5a0133c478 [AArch64] Add a few more VFP register helpers. 
Renames Is128Bit to IsQuad to line up more with the other helpers.
 2015-01-07 13:05:55 -06:00
Ryan Houdek 0a23ca9461 [AArch64] Add MUL/MNEG instruction aliases to the emitter. 2015-01-07 13:03:01 -06:00
Ryan Houdek d2eaba5cb7 [AArch64] Minor MOVI2R improvement. 
Use the ZR for both input arguments in the case the immediate is the maximum immediate value.
This allows it to be aliased to MVN when disassembling.
 2015-01-07 13:00:39 -06:00
Ryan Houdek 8dba84dd7c [AArch64] Fix 8 & 16 bit loadstore indexes. 
I wasn't bit shifting correctly for 8 and 16bit loadstores.
 2015-01-07 12:58:37 -06:00
Ryan Houdek f4f59ea71e [AArch64] Fix ADDS/SUBS emitter functions. 
These weren't emitting the flag bit. So they were regular ADD and SUB emitters.
 2015-01-07 12:56:45 -06:00
Ryan Houdek d3c2e8fb0a [AArch64] Improvements to the AArch64 emitter. 
Fixes issues with negative offsets in loadstore instructions.
Adds ADRP/ADR instructions.
Optimizes MOVI2R function to take advantage of ADRP on pointers, can change a 3 instruction operation down to one.
Adds GPR push/pop operations for ABI related things.
 2014-12-20 19:35:52 -06:00
Ryan Houdek 2c39d4044d [AArch64] Add loadstore paired emitter instructions. 2014-12-02 21:08:34 -06:00
Lioncash e9b09a4c9f Arm(64)Emitter: Make some variables static 2014-11-25 23:27:48 -05:00
Ryan Houdek 7608e3f11e Add AArch64 emitter aliases for MOV and MVN. 2014-09-18 16:30:40 -05:00