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Arm64Emitter: Mark trivial functions as constexpr

This commit is contained in:
Lioncash 2015-10-22 15:20:35 -04:00
parent dddc834c14
commit 018c85c248
2 changed files with 18 additions and 18 deletions
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12
Source/Core/Common/Arm64Emitter.cpp
View File

@ -815,32 +815,32 @@ void ARM64XEmitter::EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64
Write32((size << 30) | (0b111 << 27) | (op << 22) | ((imm & 0x1FF) << 12) | (Rn << 5) | Rt);
}
static inline bool IsInRangeImm19(s64 distance)
static constexpr bool IsInRangeImm19(s64 distance)
{
return (distance >= -0x40000 && distance <= 0x3FFFF);
}
static inline bool IsInRangeImm14(s64 distance)
static constexpr bool IsInRangeImm14(s64 distance)
{
return (distance >= -0x2000 && distance <= 0x1FFF);
}
static inline bool IsInRangeImm26(s64 distance)
static constexpr bool IsInRangeImm26(s64 distance)
{
return (distance >= -0x2000000 && distance <= 0x1FFFFFF);
}
static inline u32 MaskImm19(s64 distance)
static constexpr u32 MaskImm19(s64 distance)
{
return distance & 0x7FFFF;
}
static inline u32 MaskImm14(s64 distance)
static constexpr u32 MaskImm14(s64 distance)
{
return distance & 0x3FFF;
}
static inline u32 MaskImm26(s64 distance)
static constexpr u32 MaskImm26(s64 distance)
{
return distance & 0x3FFFFFF;
}

24
Source/Core/Common/Arm64Emitter.h
View File

@ -81,19 +81,19 @@ enum ARM64Reg
INVALID_REG = 0xFFFFFFFF
};
inline bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
inline bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
inline bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
inline bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); }
inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
inline bool IsGPR(ARM64Reg reg) { return (int)reg < 0x40; }
constexpr bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
constexpr bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
constexpr bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
constexpr bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); }
constexpr bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
constexpr bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
constexpr bool IsGPR(ARM64Reg reg) { return static_cast<int>(reg) < 0x40; }
inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); }
inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); }
inline ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return (ARM64Reg)(DecodeReg(reg) + S0); }
inline ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return (ARM64Reg)((reg & ~0xC0) | 0x80); }
inline ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return (ARM64Reg)(reg | 0xC0); }
constexpr ARM64Reg DecodeReg(ARM64Reg reg) { return static_cast<ARM64Reg>(reg & 0x1F); }
constexpr ARM64Reg EncodeRegTo64(ARM64Reg reg) { return static_cast<ARM64Reg>(reg | 0x20); }
constexpr ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return static_cast<ARM64Reg>(DecodeReg(reg) + S0); }
constexpr ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return static_cast<ARM64Reg>((reg & ~0xC0) | 0x80); }
constexpr ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return static_cast<ARM64Reg>(reg | 0xC0); }
// For AND/TST/ORR/EOR etc
bool IsImmLogical(uint64_t value, unsigned int width, unsigned int *n, unsigned int *imm_s, unsigned int *imm_r);