Arm(64)Emitter: Make some variables static
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Lioncash
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4afb85ef33
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@ -71,7 +71,7 @@ void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)
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// Exception generation
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const u32 ExcEnc[][3] = {
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static const u32 ExcEnc[][3] = {
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{0, 0, 1}, // SVC
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{0, 0, 2}, // HVC
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{0, 0, 3}, // SMC
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@ -83,13 +83,13 @@ const u32 ExcEnc[][3] = {
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};
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// Arithmetic generation
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const u32 ArithEnc[] = {
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static const u32 ArithEnc[] = {
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0x058, // ADD
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0x258, // SUB
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};
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// Conditional Select
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const u32 CondSelectEnc[][2] = {
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static const u32 CondSelectEnc[][2] = {
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{0, 0}, // CSEL
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{0, 1}, // CSINC
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{1, 0}, // CSINV
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@ -97,7 +97,7 @@ const u32 CondSelectEnc[][2] = {
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};
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// Data-Processing (1 source)
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const u32 Data1SrcEnc[][2] = {
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static const u32 Data1SrcEnc[][2] = {
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{0, 0}, // RBIT
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{0, 1}, // REV16
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{0, 2}, // REV32
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@ -107,7 +107,7 @@ const u32 Data1SrcEnc[][2] = {
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};
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// Data-Processing (2 source)
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const u32 Data2SrcEnc[] = {
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static const u32 Data2SrcEnc[] = {
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0x02, // UDIV
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0x03, // SDIV
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0x08, // LSLV
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@ -125,7 +125,7 @@ const u32 Data2SrcEnc[] = {
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};
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// Data-Processing (3 source)
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const u32 Data3SrcEnc[][2] = {
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static const u32 Data3SrcEnc[][2] = {
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{0, 0}, // MADD
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{0, 1}, // MSUB
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{1, 0}, // SMADDL (64Bit Only)
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@ -137,7 +137,7 @@ const u32 Data3SrcEnc[][2] = {
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};
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// Logical (shifted register)
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const u32 LogicalEnc[][2] = {
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static const u32 LogicalEnc[][2] = {
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{0, 0}, // AND
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{0, 1}, // BIC
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{1, 0}, // OOR
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@ -149,7 +149,7 @@ const u32 LogicalEnc[][2] = {
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};
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// Load/Store Exclusive
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u32 LoadStoreExcEnc[][5] = {
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static u32 LoadStoreExcEnc[][5] = {
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{0, 0, 0, 0, 0}, // STXRB
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{0, 0, 0, 0, 1}, // STLXRB
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{0, 0, 1, 0, 0}, // LDXRB
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@ -543,43 +543,45 @@ void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg
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// IMM, REG, IMMSREG, RSR
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// -1 for invalid if the instruction doesn't support that
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const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s)
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{17, 1, 1, 1}, // EOR(s)
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{18, 2, 2, 2}, // SUB(s)
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{19, 3, 3, 3}, // RSB(s)
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{20, 4, 4, 4}, // ADD(s)
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{21, 5, 5, 5}, // ADC(s)
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{22, 6, 6, 6}, // SBC(s)
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{23, 7, 7, 7}, // RSC(s)
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{24, 8, 8, 8}, // TST
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{25, 9, 9, 9}, // TEQ
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{26, 10, 10, 10}, // CMP
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{27, 11, 11, 11}, // CMN
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{28, 12, 12, 12}, // ORR(s)
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{29, 13, 13, 13}, // MOV(s)
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{30, 14, 14, 14}, // BIC(s)
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{31, 15, 15, 15}, // MVN(s)
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{24, -1, -1, -1}, // MOVW
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{26, -1, -1, -1}, // MOVT
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};
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static const s32 InstOps[][4] = {
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{16, 0, 0, 0}, // AND(s)
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{17, 1, 1, 1}, // EOR(s)
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{18, 2, 2, 2}, // SUB(s)
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{19, 3, 3, 3}, // RSB(s)
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{20, 4, 4, 4}, // ADD(s)
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{21, 5, 5, 5}, // ADC(s)
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{22, 6, 6, 6}, // SBC(s)
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{23, 7, 7, 7}, // RSC(s)
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{24, 8, 8, 8}, // TST
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{25, 9, 9, 9}, // TEQ
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{26, 10, 10, 10}, // CMP
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{27, 11, 11, 11}, // CMN
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{28, 12, 12, 12}, // ORR(s)
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{29, 13, 13, 13}, // MOV(s)
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{30, 14, 14, 14}, // BIC(s)
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{31, 15, 15, 15}, // MVN(s)
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{24, -1, -1, -1}, // MOVW
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{26, -1, -1, -1}, // MOVT
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};
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const char *InstNames[] = {"AND",
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"EOR",
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"SUB",
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"RSB",
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"ADD",
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"ADC",
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"SBC",
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"RSC",
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"TST",
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"TEQ",
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"CMP",
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"CMN",
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"ORR",
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"MOV",
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"BIC",
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"MVN"
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};
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static const char* InstNames[] = {
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"AND",
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"EOR",
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"SUB",
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"RSB",
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"ADD",
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"ADC",
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"SBC",
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"RSC",
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"TST",
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"TEQ",
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"CMP",
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"CMN",
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"ORR",
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"MOV",
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"BIC",
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"MVN"
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};
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void ARMXEmitter::AND (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm); }
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void ARMXEmitter::ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm, true); }
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@ -774,7 +776,7 @@ void ARMXEmitter::SVC(Operand2 op)
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// IMM, REG, IMMSREG, RSR
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// -1 for invalid if the instruction doesn't support that
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const s32 LoadStoreOps[][4] = {
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static const s32 LoadStoreOps[][4] = {
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{0x40, 0x60, 0x60, -1}, // STR
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{0x41, 0x61, 0x61, -1}, // LDR
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{0x44, 0x64, 0x64, -1}, // STRB
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@ -785,7 +787,7 @@ const s32 LoadStoreOps[][4] = {
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{ 0x5, 0x1, -1, -1}, // LDRSB
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{ 0x5, 0x1, -1, -1}, // LDRSH
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};
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const char *LoadStoreNames[] = {
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static const char* LoadStoreNames[] = {
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"STR",
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"LDR",
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"STRB",
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