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Arm64Emitter: Make RoundingMode enum an enum class 

Prevents namespace pollution and makes the enum members strongly typed.
This commit is contained in:
Lioncash 2020-12-30 20:24:41 -05:00
parent d87ec71615
commit fab2053439
4 changed files with 21 additions and 21 deletions
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24
Source/Core/Common/Arm64Emitter.cpp
View File

@ -2327,28 +2327,28 @@ void ARM64FloatEmitter::EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, Roundin
if (IsGPR(Rd))
{
// Use the encoding that transfers the result to a GPR.
bool sf = Is64Bit(Rd);
int type = IsDouble(Rn) ? 1 : 0;
const bool sf = Is64Bit(Rd);
const int type = IsDouble(Rn) ? 1 : 0;
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
int opcode = (sign ? 1 : 0);
int rmode = 0;
switch (round)
{
case ROUND_A:
case RoundingMode::A:
rmode = 0;
opcode |= 4;
break;
case ROUND_P:
case RoundingMode::P:
rmode = 1;
break;
case ROUND_M:
case RoundingMode::M:
rmode = 2;
break;
case ROUND_Z:
case RoundingMode::Z:
rmode = 3;
break;
case ROUND_N:
case RoundingMode::N:
rmode = 0;
break;
}
@ -2363,20 +2363,20 @@ void ARM64FloatEmitter::EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, Roundin
int opcode = 0;
switch (round)
{
case ROUND_A:
case RoundingMode::A:
opcode = 0x1C;
break;
case ROUND_N:
case RoundingMode::N:
opcode = 0x1A;
break;
case ROUND_M:
case RoundingMode::M:
opcode = 0x1B;
break;
case ROUND_P:
case RoundingMode::P:
opcode = 0x1A;
sz |= 2;
break;
case ROUND_Z:
case RoundingMode::Z:
opcode = 0x1B;
sz |= 2;
break;

12
Source/Core/Common/Arm64Emitter.h
View File

@ -310,13 +310,13 @@ enum ShiftAmount
SHIFT_48 = 3,
};
enum RoundingMode
enum class RoundingMode
{
ROUND_A, // round to nearest, ties to away
ROUND_M, // round towards -inf
ROUND_N, // round to nearest, ties to even
ROUND_P, // round towards +inf
ROUND_Z, // round towards zero
A, // round to nearest, ties to away
M, // round towards -inf
N, // round to nearest, ties to even
P, // round towards +inf
Z, // round towards zero
};
struct FixupBranch

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
View File

@ -335,13 +335,13 @@ void JitArm64::fctiwzx(UGeckoInstruction inst)
if (single)
{
m_float_emit.FCVTS(EncodeRegToSingle(VD), EncodeRegToSingle(VB), ROUND_Z);
m_float_emit.FCVTS(EncodeRegToSingle(VD), EncodeRegToSingle(VB), RoundingMode::Z);
}
else
{
ARM64Reg V1 = gpr.GetReg();
m_float_emit.FCVTS(V1, EncodeRegToDouble(VB), ROUND_Z);
m_float_emit.FCVTS(V1, EncodeRegToDouble(VB), RoundingMode::Z);
m_float_emit.FMOV(EncodeRegToSingle(VD), V1);
gpr.Unlock(V1);

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
View File

@ -261,7 +261,7 @@ void JitArm64::mfspr(UGeckoInstruction inst)
m_float_emit.LDR(32, INDEX_UNSIGNED, SD, Xg,
offsetof(CoreTiming::Globals, last_OC_factor_inverted));
m_float_emit.FMUL(SC, SC, SD);
m_float_emit.FCVTS(Xresult, SC, ROUND_Z);
m_float_emit.FCVTS(Xresult, SC, RoundingMode::Z);
LDP(INDEX_SIGNED, XA, XB, Xg, offsetof(CoreTiming::Globals, global_timer));
SXTW(XB, WB);