SaxxonPike
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0a7dc52aa0
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C64: BA and raster IRQ cleanup
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2019-07-09 22:41:12 -05:00 |
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SaxxonPike
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3a135c7c26
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C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ
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2019-07-09 21:40:03 -05:00 |
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SaxxonPike
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e63d10b608
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C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA
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2019-07-09 20:55:14 -05:00 |
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SaxxonPike
|
b471fdc692
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C64: The CPU can trigger VIC badlines on its own (needed for VSP)
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2019-07-09 20:53:54 -05:00 |
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SaxxonPike
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2abe832289
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C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does
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2019-07-09 20:52:51 -05:00 |
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SaxxonPike
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9758efe604
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6502X: CPU does a read or write regardless if the result is trashed, even during reset and dummy pushes
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2019-07-09 19:46:33 -05:00 |
|
alyosha-tas
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84b0917f65
|
Vectrex: Add schema and do some miscellanous clean up
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2019-07-09 20:01:45 -04:00 |
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SaxxonPike
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a8fd85157c
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VIC: Use correct color mapping for non-multicolor bitmap mode
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2019-07-09 08:02:55 -05:00 |
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SaxxonPike
|
83b6553749
|
VIC: Respect idle state background color registers, plus black in undocumented gfx mode
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2019-07-09 06:58:13 -05:00 |
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SaxxonPike
|
89fa153477
|
VIC: Resolve background color registers separately to color matrix memory
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2019-07-09 06:55:55 -05:00 |
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SaxxonPike
|
9f733d3e7a
|
VIC: More accurate pixel pipeline
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2019-07-09 05:26:26 -05:00 |
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SaxxonPike
|
3efea15038
|
6502X: When !RDY is asserted, still do other operations. Plus, do dummy reads on stack ops
|
2019-07-09 05:24:47 -05:00 |
|
alyosha-tas
|
f544c044bf
|
NES MMC3: Mapper test indicates IRQ was happening one ppu tick too late.
|
2019-07-08 08:16:43 -04:00 |
|
alyosha-tas
|
5b2ed7e4ff
|
MC6800: disassembler and cleanup
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2019-07-07 17:32:14 -04:00 |
|
alyosha-tas
|
53dd500875
|
MC6800: More cleanup
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2019-07-07 09:08:26 -04:00 |
|
alyosha-tas
|
e2014ba3f5
|
MC6800 work and MC6809 bug fix
|
2019-07-07 08:22:01 -04:00 |
|
alyosha-tas
|
a4b38aa7a5
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MC6800: Initial commit
|
2019-07-06 20:16:48 -04:00 |
|
SaxxonPike
|
d36e02045b
|
C64: Optimize the RNG for 1541 flux transitions. (same output)
|
2019-07-06 16:32:21 -05:00 |
|
SaxxonPike
|
3bf37f1c17
|
C64: No need for LagCycles anymore.
|
2019-07-06 16:29:14 -05:00 |
|
alyosha-tas
|
475702c1e8
|
Vectrex: code cleanup
|
2019-07-06 16:44:46 -04:00 |
|
alyosha-tas
|
432abb27f6
|
Vectrex: expose menues
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2019-07-06 08:56:25 -04:00 |
|
SaxxonPike
|
6ed11de85b
|
C64: Soft/Hard reset: it's about time
|
2019-07-06 01:19:58 -05:00 |
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SaxxonPike
|
d48964b642
|
6502X: According to the datasheet, RDY must be high in order for interrupts to trigger
- this has implications for C64, as it may cause VIC interrupts to fire quite later than they currently do
|
2019-07-06 00:00:51 -05:00 |
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SaxxonPike
|
400b04b690
|
C64: CIA was sometimes delaying too long to fire interrupts by 1 cycle.
- This could have implications for existing TASes (!)
|
2019-07-05 23:59:01 -05:00 |
|
SaxxonPike
|
69f8b143a3
|
C64: Foreground pixels are black when VIC is in idle state.
|
2019-07-05 21:05:38 -05:00 |
|
SaxxonPike
|
8698aa41be
|
Merge branch 'master' into c64-refactor
|
2019-07-05 20:14:28 -05:00 |
|
alyosha-tas
|
9cbc78778f
|
Vectrex: interrupt fixes
|
2019-07-05 20:25:03 -04:00 |
|
alyosha-tas
|
6a5fc8b47e
|
Vectrex: Implement interrupts, fixes Bedlam
|
2019-07-05 19:57:55 -04:00 |
|
alyosha-tas
|
b0123ea133
|
Vectrex: fix control stick in some cases
|
2019-07-05 17:16:11 -04:00 |
|
alyosha-tas
|
e9ca6f82bc
|
Trace Logger: Fix exception when scrolling
|
2019-07-05 10:06:00 -04:00 |
|
alyosha-tas
|
275ccb381a
|
Vectrex: ramp overscan more accurate, fixes numerous display bugs
|
2019-07-04 21:26:13 -04:00 |
|
alyosha-tas
|
9b2d926bc0
|
Vectrex: working controllers
|
2019-07-04 20:00:59 -04:00 |
|
SaxxonPike
|
49b613962e
|
C64: Fix a typo disabling voice 3 when high pass filter is set
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2019-07-04 17:32:35 -05:00 |
|
SaxxonPike
|
f45e934fec
|
C64: Reset the SID filter on hard reset.
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2019-07-04 17:24:22 -05:00 |
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SaxxonPike
|
579ffe5c25
|
C64: Had the flag with the wrong polarity. Thanks, C64Anabalt.
|
2019-07-04 14:20:12 -05:00 |
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SaxxonPike
|
691577499f
|
C64: When a sprite is eligible for display, initialize it with the correct crunch state based on Y expansion
|
2019-07-04 14:12:46 -05:00 |
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SaxxonPike
|
36ac592193
|
C64: Individual IRQ flags for S/S or S/D collisions are always set even if not eligible to assert IRQ externally
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2019-07-04 13:59:41 -05:00 |
|
SaxxonPike
|
5c9445fb96
|
C64: Reuse some local memory in the sprite renderer.
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2019-07-04 12:47:09 -05:00 |
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SaxxonPike
|
55145ff7ba
|
C64: The T64 format was never supported, but at least make the core aware of it
|
2019-07-04 12:46:28 -05:00 |
|
SaxxonPike
|
2c804cab34
|
C64: Fix a function ambiguity in the CIA class.
|
2019-07-04 00:51:19 -05:00 |
|
SaxxonPike
|
2dd80eb0f4
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C64: Implement more CIA features and CIA/VIA defaults.
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2019-07-04 00:31:48 -05:00 |
|
SaxxonPike
|
32d59e8514
|
C64: Implement more VIA features.
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2019-07-04 00:23:11 -05:00 |
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SaxxonPike
|
7fbccb7a46
|
C64: Use write protection on G64 images (which are often copy protected), and disable it on D64 images.
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2019-07-04 00:14:21 -05:00 |
|
SaxxonPike
|
4e1892d094
|
C64: Allow writing to disk.
|
2019-07-04 00:11:03 -05:00 |
|
SaxxonPike
|
0cdb28fc8f
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C64: Format D64 sector headers with directory ID instead of A0/A0.
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2019-07-04 00:03:50 -05:00 |
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SaxxonPike
|
ceb1338459
|
C64: Use proper sector gaps based on density when converting from D64.
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2019-07-04 00:02:28 -05:00 |
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SaxxonPike
|
e74dfe15a8
|
C64: VIA PB7 output timing adjusted to match datasheet.
|
2019-07-04 00:00:05 -05:00 |
|
SaxxonPike
|
cb48104d7a
|
6502X: Fix ADC with decimal mode enabled.
|
2019-07-03 23:49:55 -05:00 |
|
alyosha-tas
|
95db4f2159
|
Vectrex: add pcm sample playback
|
2019-07-03 20:49:27 -04:00 |
|
alyosha-tas
|
38772dcd89
|
Vectrex: fix dumb cpu copy paste, fixes scramble and probably others
|
2019-07-02 20:33:43 -04:00 |