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Vectrex: fix dumb cpu copy paste, fixes scramble and probably others

This commit is contained in:
alyosha-tas 2019-07-02 20:33:43 -04:00
parent c5c4c45596
commit 38772dcd89
1 changed files with 3 additions and 3 deletions
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6
BizHawk.Emulation.Cores/CPUs/MC6809/Operations.cs
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@ -167,7 +167,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
Reg16_d += (Regs[src] & 0xF);
FlagH = Reg16_d.Bit(4);
FlagV = (Regs[dest].Bit(7) != Regs[src].Bit(7)) && (Regs[dest].Bit(7) != ans.Bit(7));
FlagV = (Regs[dest].Bit(7) == Regs[src].Bit(7)) && (Regs[dest].Bit(7) != ans.Bit(7));
FlagN = ans > 127;
Regs[dest] = ans;
@ -400,7 +400,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
Reg16_d += ((Regs[src] & 0xF) + c);
FlagH = Reg16_d.Bit(4);
FlagV = (Regs[dest].Bit(7) != Regs[src].Bit(7)) && (Regs[dest].Bit(7) != ans.Bit(7));
FlagV = (Regs[dest].Bit(7) == Regs[src].Bit(7)) && (Regs[dest].Bit(7) != ans.Bit(7));
FlagN = false;
Regs[dest] = ans;
@ -486,7 +486,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
ushort ans = (ushort)(Reg16_d & 0xFFFF);
FlagN = ans > 0x7FFF;
FlagV = (D.Bit(15) != Regs[src].Bit(15)) && (D.Bit(15) != ans.Bit(15));
FlagV = (D.Bit(15) == Regs[src].Bit(15)) && (D.Bit(15) != ans.Bit(15));
D = ans;
}