2019-03-30 21:09:04 +00:00
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using System;
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2020-01-12 21:18:22 +00:00
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namespace BizHawk.Emulation.Cores.Components.MC6809
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2019-03-30 21:09:04 +00:00
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{
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public partial class MC6809
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{
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2019-04-06 20:16:53 +00:00
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public ulong TotalExecutedCycles;
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2019-03-30 21:09:04 +00:00
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// variables for executing instructions
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public int instr_pntr = 0;
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2019-04-08 23:57:21 +00:00
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public ushort[] cur_instr = new ushort[60];
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public int opcode_see;
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2019-04-07 20:57:24 +00:00
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public int IRQS;
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public int irq_pntr;
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2019-03-30 21:09:04 +00:00
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2019-04-08 23:57:21 +00:00
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ushort reg_d_ad;
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ushort reg_h_ad;
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ushort reg_l_ad;
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2019-03-30 21:09:04 +00:00
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public void FetchInstruction(byte opcode)
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{
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2019-04-08 23:57:21 +00:00
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opcode_see = opcode;
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2019-03-30 21:09:04 +00:00
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switch (opcode)
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{
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case 0x00: DIRECT_MEM(NEG); break; // NEG (Direct)
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case 0x01: ILLEGAL(); break; // ILLEGAL
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case 0x02: ILLEGAL(); break; // ILLEGAL
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case 0x03: DIRECT_MEM(COM); break; // COM (Direct)
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case 0x04: DIRECT_MEM(LSR); break; // LSR (Direct)
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case 0x05: ILLEGAL(); break; // ILLEGAL
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case 0x06: DIRECT_MEM(ROR); break; // ROR (Direct)
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case 0x07: DIRECT_MEM(ASR); break; // ASR (Direct)
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case 0x08: DIRECT_MEM(ASL); break; // ASL , LSL (Direct)
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case 0x09: DIRECT_MEM(ROL); break; // ROL (Direct)
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case 0x0A: DIRECT_MEM(DEC8); break; // DEC (Direct)
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case 0x0B: ILLEGAL(); break; // ILLEGAL
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case 0x0C: DIRECT_MEM(INC8); break; // INC (Direct)
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case 0x0D: DIRECT_MEM(TST); break; // TST (Direct)
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case 0x0E: JMP_DIR_(); break; // JMP (Direct)
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case 0x0F: DIRECT_MEM(CLR); break; // CLR (Direct)
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case 0x10: PAGE_2(); break; // Page 2
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case 0x11: PAGE_3(); break; // Page 3
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case 0x12: NOP_(); break; // NOP (Inherent)
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case 0x13: SYNC_(); break; // SYNC (Inherent)
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case 0x14: ILLEGAL(); break; // ILLEGAL
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case 0x15: ILLEGAL(); break; // ILLEGAL
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case 0x16: LBR_(true); break; // LBRA (Relative)
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case 0x17: LBSR_(); break; // LBSR (Relative)
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case 0x18: ILLEGAL(); break; // ILLEGAL
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case 0x19: REG_OP(DA, A); break; // DAA (Inherent)
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case 0x1A: REG_OP_IMD_CC(OR8); break; // ORCC (Immediate)
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case 0x1B: ILLEGAL(); break; // ILLEGAL
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case 0x1C: REG_OP_IMD_CC(AND8); break; // ANDCC (Immediate)
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case 0x1D: REG_OP(SEX, A); break; // SEX (Inherent)
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case 0x1E: EXG_(); break; // EXG (Immediate)
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case 0x1F: TFR_(); break; // TFR (Immediate)
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case 0x20: BR_(true); break; // BRA (Relative)
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case 0x21: BR_(false); break; // BRN (Relative)
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case 0x22: BR_(!(FlagC | FlagZ)); break; // BHI (Relative)
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case 0x23: BR_(FlagC | FlagZ); break; // BLS (Relative)
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case 0x24: BR_(!FlagC); break; // BHS , BCC (Relative)
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case 0x25: BR_(FlagC); break; // BLO , BCS (Relative)
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case 0x26: BR_(!FlagZ); break; // BNE (Relative)
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case 0x27: BR_(FlagZ); break; // BEQ (Relative)
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case 0x28: BR_(!FlagV); break; // BVC (Relative)
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case 0x29: BR_(FlagV); break; // BVS (Relative)
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case 0x2A: BR_(!FlagN); break; // BPL (Relative)
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case 0x2B: BR_(FlagN); break; // BMI (Relative)
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case 0x2C: BR_(FlagN == FlagV); break; // BGE (Relative)
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case 0x2D: BR_(FlagN ^ FlagV); break; // BLT (Relative)
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case 0x2E: BR_((!FlagZ) & (FlagN == FlagV)); break; // BGT (Relative)
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case 0x2F: BR_(FlagZ | (FlagN ^ FlagV)); break; // BLE (Relative)
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2019-03-31 21:33:02 +00:00
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case 0x30: INDEX_OP(LEAX); break; // LEAX (Indexed)
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case 0x31: INDEX_OP(LEAY); break; // LEAY (Indexed)
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case 0x32: INDEX_OP(LEAS); break; // LEAS (Indexed)
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case 0x33: INDEX_OP(LEAU); break; // LEAU (Indexed)
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2019-04-02 00:00:54 +00:00
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case 0x34: PSH(SP); break; // PSHS (Immediate)
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2019-04-03 00:25:48 +00:00
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case 0x35: PUL(SP); break; // PULS (Immediate)
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2019-04-02 00:00:54 +00:00
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case 0x36: PSH(US); break; // PSHU (Immediate)
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2019-04-03 00:25:48 +00:00
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case 0x37: PUL(US); break; // PULU (Immediate)
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2019-03-30 21:09:04 +00:00
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case 0x38: ILLEGAL(); break; // ILLEGAL
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2019-03-31 13:27:51 +00:00
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case 0x39: RTS(); break; // RTS (Inherent)
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case 0x3A: ABX_(); break; // ABX (Inherent)
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case 0x3B: RTI(); break; // RTI (Inherent)
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2019-04-03 00:25:48 +00:00
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case 0x3C: CWAI_(); break; // CWAI (Inherent)
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2019-03-31 13:27:51 +00:00
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case 0x3D: MUL_(); break; // MUL (Inherent)
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2019-03-30 21:09:04 +00:00
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case 0x3E: ILLEGAL(); break; // ILLEGAL
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2019-04-03 00:25:48 +00:00
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case 0x3F: SWI1(); break; // SWI (Inherent)
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2019-03-30 21:09:04 +00:00
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case 0x40: REG_OP(NEG, A); break; // NEGA (Inherent)
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case 0x41: ILLEGAL(); break; // ILLEGAL
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case 0x42: ILLEGAL(); break; // ILLEGAL
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case 0x43: REG_OP(COM, A); break; // COMA (Inherent)
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case 0x44: REG_OP(LSR, A); break; // LSRA (Inherent)
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case 0x45: ILLEGAL(); break; // ILLEGAL
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case 0x46: REG_OP(ROR, A); break; // RORA (Inherent)
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case 0x47: REG_OP(ASR, A); break; // ASRA (Inherent)
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case 0x48: REG_OP(ASL, A); break; // ASLA , LSLA (Inherent)
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case 0x49: REG_OP(ROL, A); break; // ROLA (Inherent)
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case 0x4A: REG_OP(DEC8, A); break; // DECA (Inherent)
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case 0x4B: ILLEGAL(); break; // ILLEGAL
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case 0x4C: REG_OP(INC8, A); break; // INCA (Inherent)
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case 0x4D: REG_OP(TST, A); break; // TSTA (Inherent)
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case 0x4E: ILLEGAL(); break; // ILLEGAL
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case 0x4F: REG_OP(CLR, A); break; // CLRA (Inherent)
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case 0x50: REG_OP(NEG, B); break; // NEGB (Inherent)
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case 0x51: ILLEGAL(); break; // ILLEGAL
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case 0x52: ILLEGAL(); break; // ILLEGAL
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case 0x53: REG_OP(COM, B); break; // COMB (Inherent)
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case 0x54: REG_OP(LSR, B); break; // LSRB (Inherent)
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case 0x55: ILLEGAL(); break; // ILLEGAL
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case 0x56: REG_OP(ROR, B); break; // RORB (Inherent)
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case 0x57: REG_OP(ASR, B); break; // ASRB (Inherent)
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case 0x58: REG_OP(ASL, B); break; // ASLB , LSLB (Inherent)
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case 0x59: REG_OP(ROL, B); break; // ROLB (Inherent)
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case 0x5A: REG_OP(DEC8, B); break; // DECB (Inherent)
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case 0x5B: ILLEGAL(); break; // ILLEGAL
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case 0x5C: REG_OP(INC8, B); break; // INCB (Inherent)
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case 0x5D: REG_OP(TST, B); break; // TSTB (Inherent)
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case 0x5E: ILLEGAL(); break; // ILLEGAL
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case 0x5F: REG_OP(CLR, B); break; // CLRB (Inherent)
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2019-04-03 00:25:48 +00:00
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case 0x60: INDEX_OP(I_NEG); break; // NEG (Indexed)
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2019-03-30 21:09:04 +00:00
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case 0x61: ILLEGAL(); break; // ILLEGAL
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case 0x62: ILLEGAL(); break; // ILLEGAL
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2019-04-03 00:25:48 +00:00
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case 0x63: INDEX_OP(I_COM); break; // COM (Indexed)
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case 0x64: INDEX_OP(I_LSR); break; // LSR (Indexed)
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2019-03-30 21:09:04 +00:00
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case 0x65: ILLEGAL(); break; // ILLEGAL
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2019-04-03 00:25:48 +00:00
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case 0x66: INDEX_OP(I_ROR); break; // ROR (Indexed)
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case 0x67: INDEX_OP(I_ASR); break; // ASR (Indexed)
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case 0x68: INDEX_OP(I_ASL); break; // ASL , LSL (Indexed)
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case 0x69: INDEX_OP(I_ROL); break; // ROL (Indexed)
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case 0x6A: INDEX_OP(I_DEC); break; // DEC (Indexed)
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2019-03-30 21:09:04 +00:00
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case 0x6B: ILLEGAL(); break; // ILLEGAL
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2019-04-03 00:25:48 +00:00
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case 0x6C: INDEX_OP(I_INC); break; // INC (Indexed)
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case 0x6D: INDEX_OP(I_TST); break; // TST (Indexed)
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case 0x6E: INDEX_OP(I_JMP); break; // JMP (Indexed)
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case 0x6F: INDEX_OP(I_CLR); break; // CLR (Indexed)
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2019-03-31 13:27:51 +00:00
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case 0x70: EXT_MEM(NEG); break; // NEG (Extended)
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2019-03-30 21:09:04 +00:00
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case 0x71: ILLEGAL(); break; // ILLEGAL
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case 0x72: ILLEGAL(); break; // ILLEGAL
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2019-03-31 13:27:51 +00:00
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case 0x73: EXT_MEM(COM); break; // COM (Extended)
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case 0x74: EXT_MEM(LSR); break; // LSR (Extended)
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2019-03-30 21:09:04 +00:00
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case 0x75: ILLEGAL(); break; // ILLEGAL
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2019-03-31 13:27:51 +00:00
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case 0x76: EXT_MEM(ROR); break; // ROR (Extended)
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case 0x77: EXT_MEM(ASR); break; // ASR (Extended)
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case 0x78: EXT_MEM(ASL); break; // ASL , LSL (Extended)
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case 0x79: EXT_MEM(ROL); break; // ROL (Extended)
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case 0x7A: EXT_MEM(DEC8); break; // DEC (Extended)
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2019-03-30 21:09:04 +00:00
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case 0x7B: ILLEGAL(); break; // ILLEGAL
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2019-03-31 13:27:51 +00:00
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case 0x7C: EXT_MEM(INC8); break; // INC (Extended)
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case 0x7D: EXT_MEM(TST); break; // TST (Extended)
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case 0x7E: JMP_EXT_(); break; // JMP (Extended)
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case 0x7F: EXT_MEM(CLR); break; // CLR (Extended)
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2019-04-04 00:22:23 +00:00
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case 0x80: REG_OP_IMD(SUB8, A); break; // SUBA (Immediate)
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case 0x81: REG_OP_IMD(CMP8, A); break; // CMPA (Immediate)
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case 0x82: REG_OP_IMD(SBC8, A); break; // SBCA (Immediate)
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case 0x83: IMD_OP_D(SUB16, D); break; // SUBD (Immediate)
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case 0x84: REG_OP_IMD(AND8, A); break; // ANDA (Immediate)
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case 0x85: REG_OP_IMD(BIT, A); break; // BITA (Immediate)
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2019-06-01 16:25:30 +00:00
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case 0x86: REG_OP_IMD(LD_8, A); break; // LDA (Immediate)
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2019-03-30 21:09:04 +00:00
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case 0x87: ILLEGAL(); break; // ILLEGAL
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2019-04-04 00:22:23 +00:00
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case 0x88: REG_OP_IMD(XOR8, A); break; // EORA (Immediate)
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case 0x89: REG_OP_IMD(ADC8, A); break; // ADCA (Immediate)
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case 0x8A: REG_OP_IMD(OR8, A); break; // ORA (Immediate)
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case 0x8B: REG_OP_IMD(ADD8, A); break; // ADDA (Immediate)
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2019-04-06 20:16:53 +00:00
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case 0x8C: IMD_CMP_16(CMP16, X); break; // CMPX (Immediate)
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2019-04-04 00:22:23 +00:00
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case 0x8D: BSR_(); break; // BSR (Relative)
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case 0x8E: REG_OP_LD_16(X); break; // LDX (Immediate)
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2019-03-30 21:09:04 +00:00
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case 0x8F: ILLEGAL(); break; // ILLEGAL
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2019-04-04 00:22:23 +00:00
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case 0x90: DIRECT_MEM_4(SUB8, A); break; // SUBA (Direct)
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case 0x91: DIRECT_MEM_4(CMP8, A); break; // CMPA (Direct)
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case 0x92: DIRECT_MEM_4(SBC8, A); break; // SBCA (Direct)
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case 0x93: DIR_OP_D(SUB16, D); break; // SUBD (Direct)
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case 0x94: DIRECT_MEM_4(AND8, A); break; // ANDA (Direct)
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case 0x95: DIRECT_MEM_4(BIT, A); break; // BITA (Direct)
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2019-06-01 16:25:30 +00:00
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case 0x96: DIRECT_MEM_4(LD_8, A); break; // LDA (Direct)
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2019-04-04 00:22:23 +00:00
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case 0x97: DIRECT_ST_4(A); break; // STA (Direct)
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case 0x98: DIRECT_MEM_4(XOR8, A); break; // EORA (Direct)
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case 0x99: DIRECT_MEM_4(ADC8, A); break; // ADCA (Direct)
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case 0x9A: DIRECT_MEM_4(OR8, A); break; // ORA (Direct)
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case 0x9B: DIRECT_MEM_4(ADD8, A); break; // ADDA (Direct)
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case 0x9C: DIR_CMP_16(CMP16, X); break; // CMPX (Direct)
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2019-07-07 12:22:01 +00:00
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case 0x9D: JSR_(); break; // JSR (Direct)
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2019-04-06 15:06:23 +00:00
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case 0x9E: DIR_OP_LD_16(X); break; // LDX (Direct)
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case 0x9F: DIR_OP_ST_16(X); break; // STX (Direct)
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case 0xA0: INDEX_OP_REG(I_SUB, A); break; // SUBA (Indexed)
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case 0xA1: INDEX_OP_REG(I_CMP, A); break; // CMPA (Indexed)
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case 0xA2: INDEX_OP_REG(I_SBC, A); break; // SBCA (Indexed)
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case 0xA3: INDEX_OP_REG(I_SUBD, D); break; // SUBD (Indexed)
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case 0xA4: INDEX_OP_REG(I_AND, A); break; // ANDA (Indexed)
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case 0xA5: INDEX_OP_REG(I_BIT, A); break; // BITA (Indexed)
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case 0xA6: INDEX_OP_REG(I_LD, A); break; // LDA (Indexed)
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case 0xA7: INDEX_OP_REG(I_ST, A); break; // STA (Indexed)
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case 0xA8: INDEX_OP_REG(I_XOR, A); break; // EORA (Indexed)
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case 0xA9: INDEX_OP_REG(I_ADC, A); break; // ADCA (Indexed)
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case 0xAA: INDEX_OP_REG(I_OR, A); break; // ORA (Indexed)
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case 0xAB: INDEX_OP_REG(I_ADD, A); break; // ADDA (Indexed)
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case 0xAC: INDEX_OP_REG(I_CMP16, X); break; // CMPX (Indexed)
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case 0xAD: INDEX_OP(I_JSR); break; // JSR (Indexed)
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case 0xAE: INDEX_OP_REG(I_LD16, X); break; // LDX (Indexed)
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case 0xAF: INDEX_OP_REG(I_ST16, X); break; // STX (Indexed)
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case 0xB0: EXT_REG(SUB8, A); break; // SUBA (Extended)
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case 0xB1: EXT_REG(CMP8, A); break; // CMPA (Extended)
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case 0xB2: EXT_REG(SBC8, A); break; // SBCA (Extended)
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case 0xB3: EXT_OP_D(SUB16, D); break; // SUBD (Extended)
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|
|
case 0xB4: EXT_REG(AND8, A); break; // ANDA (Extended)
|
|
|
|
|
case 0xB5: EXT_REG(BIT, A); break; // BITA (Extended)
|
2019-06-01 16:25:30 +00:00
|
|
|
case 0xB6: EXT_REG(LD_8, A); break; // LDA (Extended)
|
2019-04-06 15:06:23 +00:00
|
|
|
case 0xB7: EXT_ST(A); break; // STA (Extended)
|
|
|
|
|
case 0xB8: EXT_REG(XOR8, A); break; // EORA (Extended)
|
|
|
|
|
case 0xB9: EXT_REG(ADC8, A); break; // ADCA (Extended)
|
|
|
|
|
case 0xBA: EXT_REG(OR8, A); break; // ORA (Extended)
|
|
|
|
|
case 0xBB: EXT_REG(ADD8, A); break; // ADDA (Extended)
|
|
|
|
|
case 0xBC: EXT_CMP_16(CMP16, X); break; // CMPX (Extended)
|
|
|
|
|
case 0xBD: JSR_EXT(); break; // JSR (Extended)
|
|
|
|
|
case 0xBE: EXT_OP_LD_16(X); break; // LDX (Extended)
|
|
|
|
|
case 0xBF: EXT_OP_ST_16(X); break; // STX (Extended)
|
2019-04-04 00:22:23 +00:00
|
|
|
case 0xC0: REG_OP_IMD(SUB8, B); break; // SUBB (Immediate)
|
|
|
|
|
case 0xC1: REG_OP_IMD(CMP8, B); break; // CMPB (Immediate)
|
|
|
|
|
case 0xC2: REG_OP_IMD(SBC8, B); break; // SBCB (Immediate)
|
|
|
|
|
case 0xC3: IMD_OP_D(ADD16, D); break; // ADDD (Immediate)
|
|
|
|
|
case 0xC4: REG_OP_IMD(AND8, B); break; // ANDB (Immediate)
|
|
|
|
|
case 0xC5: REG_OP_IMD(BIT, B); break; // BITB (Immediate)
|
2019-06-01 16:25:30 +00:00
|
|
|
case 0xC6: REG_OP_IMD(LD_8, B); break; // LDB (Immediate)
|
2019-03-30 21:09:04 +00:00
|
|
|
case 0xC7: ILLEGAL(); break; // ILLEGAL
|
2019-04-04 00:22:23 +00:00
|
|
|
case 0xC8: REG_OP_IMD(XOR8, B); break; // EORB (Immediate)
|
|
|
|
|
case 0xC9: REG_OP_IMD(ADC8, B); break; // ADCB (Immediate)
|
|
|
|
|
case 0xCA: REG_OP_IMD(OR8, B); break; // ORB (Immediate)
|
|
|
|
|
case 0xCB: REG_OP_IMD(ADD8, B); break; // ADDB (Immediate)
|
2019-04-06 15:06:23 +00:00
|
|
|
case 0xCC: REG_OP_LD_16D(); break; // LDD (Immediate)
|
2019-03-30 21:09:04 +00:00
|
|
|
case 0xCD: ILLEGAL(); break; // ILLEGAL
|
2019-04-04 00:22:23 +00:00
|
|
|
case 0xCE: REG_OP_LD_16(US); break; // LDU (Immediate)
|
2019-03-30 21:09:04 +00:00
|
|
|
case 0xCF: ILLEGAL(); break; // ILLEGAL
|
2019-04-04 00:22:23 +00:00
|
|
|
case 0xD0: DIRECT_MEM_4(SUB8, B); break; // SUBB (Direct)
|
|
|
|
|
case 0xD1: DIRECT_MEM_4(CMP8, B); break; // CMPB (Direct)
|
|
|
|
|
case 0xD2: DIRECT_MEM_4(SBC8, B); break; // SBCB (Direct)
|
|
|
|
|
case 0xD3: DIR_OP_D(ADD16, D); break; // ADDD (Direct)
|
|
|
|
|
case 0xD4: DIRECT_MEM_4(AND8, B); break; // ANDB (Direct)
|
|
|
|
|
case 0xD5: DIRECT_MEM_4(BIT, B); break; // BITB (Direct)
|
2019-06-01 16:25:30 +00:00
|
|
|
case 0xD6: DIRECT_MEM_4(LD_8, B); break; // LDB (Direct)
|
2019-04-04 00:22:23 +00:00
|
|
|
case 0xD7: DIRECT_ST_4(B); break; // STB (Direct)
|
|
|
|
|
case 0xD8: DIRECT_MEM_4(XOR8, B); break; // EORB (Direct)
|
|
|
|
|
case 0xD9: DIRECT_MEM_4(ADC8, B); break; // ADCB (Direct)
|
|
|
|
|
case 0xDA: DIRECT_MEM_4(OR8, B); break; // ORB (Direct)
|
|
|
|
|
case 0xDB: DIRECT_MEM_4(ADD8, B); break; // ADDB (Direct)
|
2019-04-06 15:06:23 +00:00
|
|
|
case 0xDC: DIR_OP_LD_16D(); break; // LDD (Direct)
|
|
|
|
|
case 0xDD: DIR_OP_ST_16D(); break; // STD (Direct)
|
|
|
|
|
case 0xDE: DIR_OP_LD_16(US); break; // LDU (Direct)
|
|
|
|
|
case 0xDF: DIR_OP_ST_16(US); break; // STU (Direct)
|
|
|
|
|
case 0xE0: INDEX_OP_REG(I_SUB, B); break; // SUBB (Indexed)
|
|
|
|
|
case 0xE1: INDEX_OP_REG(I_CMP, B); break; // CMPB (Indexed)
|
|
|
|
|
case 0xE2: INDEX_OP_REG(I_SBC, B); break; // SBCB (Indexed)
|
|
|
|
|
case 0xE3: INDEX_OP_REG(I_ADDD, D); break; // ADDD (Indexed)
|
|
|
|
|
case 0xE4: INDEX_OP_REG(I_AND, B); break; // ANDB (Indexed)
|
|
|
|
|
case 0xE5: INDEX_OP_REG(I_BIT, B); break; // BITB (Indexed)
|
|
|
|
|
case 0xE6: INDEX_OP_REG(I_LD, B); break; // LDB (Indexed)
|
|
|
|
|
case 0xE7: INDEX_OP_REG(I_ST, B); break; // STB (Indexed)
|
|
|
|
|
case 0xE8: INDEX_OP_REG(I_XOR, B); break; // EORB (Indexed)
|
|
|
|
|
case 0xE9: INDEX_OP_REG(I_ADC, B); break; // ADCB (Indexed)
|
|
|
|
|
case 0xEA: INDEX_OP_REG(I_OR, B); break; // ORB (Indexed)
|
|
|
|
|
case 0xEB: INDEX_OP_REG(I_ADD, B); break; // ADDB (Indexed)
|
|
|
|
|
case 0xEC: INDEX_OP_REG(I_LD16D, D); break; // LDD (Indexed)
|
|
|
|
|
case 0xED: INDEX_OP_REG(I_ST16D, D); break; // STD (Indexed)
|
|
|
|
|
case 0xEE: INDEX_OP_REG(I_LD16, US); break; // LDU (Indexed)
|
|
|
|
|
case 0xEF: INDEX_OP_REG(I_ST16, US); break; // STU (Indexed)
|
|
|
|
|
case 0xF0: EXT_REG(SUB8, B); break; // SUBB (Extended)
|
|
|
|
|
case 0xF1: EXT_REG(CMP8, B); break; // CMPB (Extended)
|
|
|
|
|
case 0xF2: EXT_REG(SBC8, B); break; // SBCB (Extended)
|
|
|
|
|
case 0xF3: EXT_OP_D(ADD16, D); break; // ADDD (Extended)
|
|
|
|
|
case 0xF4: EXT_REG(AND8, B); break; // ANDB (Extended)
|
|
|
|
|
case 0xF5: EXT_REG(BIT, B); break; // BITB (Extended)
|
2019-06-01 16:25:30 +00:00
|
|
|
case 0xF6: EXT_REG(LD_8, B); break; // LDB (Extended)
|
2019-04-06 15:06:23 +00:00
|
|
|
case 0xF7: EXT_ST(B); break; // STB (Extended)
|
|
|
|
|
case 0xF8: EXT_REG(XOR8, B); break; // EORB (Extended)
|
|
|
|
|
case 0xF9: EXT_REG(ADC8, B); break; // ADCB (Extended)
|
|
|
|
|
case 0xFA: EXT_REG(OR8, B); break; // ORB (Extended)
|
|
|
|
|
case 0xFB: EXT_REG(ADD8, B); break; // ADDB (Extended)
|
|
|
|
|
case 0xFC: EXT_OP_LD_16D(); break; // LDD (Extended)
|
|
|
|
|
case 0xFD: EXT_OP_ST_16D(); break; // STD (Extended)
|
|
|
|
|
case 0xFE: EXT_OP_LD_16(US); break; // LDU (Extended)
|
|
|
|
|
case 0xFF: EXT_OP_ST_16(US); break; // STU (Extended)
|
2019-03-30 21:09:04 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public void FetchInstruction2(byte opcode)
|
|
|
|
|
{
|
2019-04-08 23:57:21 +00:00
|
|
|
opcode_see = opcode;
|
2019-03-30 21:09:04 +00:00
|
|
|
switch (opcode)
|
|
|
|
|
{
|
2019-04-06 20:16:53 +00:00
|
|
|
case 0x21: LBR_(false); break; // BRN (Relative)
|
|
|
|
|
case 0x22: LBR_(!(FlagC | FlagZ)); break; // BHI (Relative)
|
|
|
|
|
case 0x23: LBR_(FlagC | FlagZ); break; // BLS (Relative)
|
|
|
|
|
case 0x24: LBR_(!FlagC); break; // BHS , BCC (Relative)
|
|
|
|
|
case 0x25: LBR_(FlagC); break; // BLO , BCS (Relative)
|
|
|
|
|
case 0x26: LBR_(!FlagZ); break; // BNE (Relative)
|
|
|
|
|
case 0x27: LBR_(FlagZ); break; // BEQ (Relative)
|
|
|
|
|
case 0x28: LBR_(!FlagV); break; // BVC (Relative)
|
|
|
|
|
case 0x29: LBR_(FlagV); break; // BVS (Relative)
|
|
|
|
|
case 0x2A: LBR_(!FlagN); break; // BPL (Relative)
|
|
|
|
|
case 0x2B: LBR_(FlagN); break; // BMI (Relative)
|
|
|
|
|
case 0x2C: LBR_(FlagN == FlagV); break; // BGE (Relative)
|
|
|
|
|
case 0x2D: LBR_(FlagN ^ FlagV); break; // BLT (Relative)
|
|
|
|
|
case 0x2E: LBR_((!FlagZ) & (FlagN == FlagV)); break; // BGT (Relative)
|
|
|
|
|
case 0x2F: LBR_(FlagZ | (FlagN ^ FlagV)); break; // BLE (Relative)
|
|
|
|
|
case 0x3F: SWI2_3(2); break; // SWI2 (Inherent)
|
|
|
|
|
case 0x83: IMD_OP_D(CMP16D, D); break; // CMPD (Immediate)
|
|
|
|
|
case 0x8C: IMD_CMP_16(CMP16, Y); break; // CMPY (Immediate)
|
|
|
|
|
case 0x8E: REG_OP_LD_16(Y); break; // LDY (Immediate)
|
|
|
|
|
case 0x93: DIR_OP_D(CMP16D, D); break; // CMPD (Direct)
|
|
|
|
|
case 0x9C: DIR_CMP_16(CMP16, Y); break; // CMPY (Direct)
|
|
|
|
|
case 0x9E: DIR_OP_LD_16(Y); break; // LDY (Direct)
|
|
|
|
|
case 0x9F: DIR_OP_ST_16(Y); break; // STY (Direct)
|
|
|
|
|
case 0xA3: INDEX_OP_REG(I_CMP16D, D); break; // CMPD (Indexed)
|
|
|
|
|
case 0xAC: INDEX_OP_REG(I_CMP16, Y); break; // CMPY (Indexed)
|
|
|
|
|
case 0xAE: INDEX_OP_REG(I_LD16, Y); break; // LDY (Indexed)
|
|
|
|
|
case 0xAF: INDEX_OP_REG(I_ST16, Y); break; // STY (Indexed)
|
|
|
|
|
case 0xB3: EXT_OP_D(CMP16D, D); break; // CMPD (Extended)
|
|
|
|
|
case 0xBC: EXT_CMP_16(CMP16, Y); break; // CMPY (Extended)
|
|
|
|
|
case 0xBE: EXT_OP_LD_16(Y); break; // LDY (Extended)
|
|
|
|
|
case 0xBF: EXT_OP_ST_16(Y); break; // STY (Extended)
|
|
|
|
|
case 0xCE: REG_OP_LD_16(SP); break; // LDS (Immediate)
|
|
|
|
|
case 0xDE: DIR_OP_LD_16(SP); break; // LDS (Direct)
|
|
|
|
|
case 0xDF: DIR_OP_ST_16(SP); break; // STS (Direct)
|
|
|
|
|
case 0xEE: INDEX_OP_REG(I_LD16, SP); break; // LDS (Indexed)
|
|
|
|
|
case 0xEF: INDEX_OP_REG(I_ST16, SP); break; // STS (Indexed)
|
|
|
|
|
case 0xFE: EXT_OP_LD_16(SP); break; // LDS (Extended)
|
|
|
|
|
case 0xFF: EXT_OP_ST_16(SP); break; // STS (Extended)
|
2019-03-30 21:09:04 +00:00
|
|
|
|
|
|
|
|
default: ILLEGAL(); break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public void FetchInstruction3(byte opcode)
|
|
|
|
|
{
|
2019-04-08 23:57:21 +00:00
|
|
|
opcode_see = opcode;
|
2019-03-30 21:09:04 +00:00
|
|
|
switch (opcode)
|
|
|
|
|
{
|
2019-04-06 20:16:53 +00:00
|
|
|
case 0x3F: SWI2_3(3); break; // SWI3 (Inherent)
|
|
|
|
|
case 0x83: IMD_CMP_16(CMP16, US); break; // CMPU (Immediate)
|
|
|
|
|
case 0x8C: IMD_CMP_16(CMP16, SP); break; // CMPS (Immediate)
|
|
|
|
|
case 0x93: DIR_CMP_16(CMP16, US); break; // CMPU (Direct)
|
|
|
|
|
case 0x9C: DIR_CMP_16(CMP16, SP); break; // CMPS (Direct)
|
|
|
|
|
case 0xA3: INDEX_OP_REG(I_CMP16, US); break; // CMPU (Indexed)
|
|
|
|
|
case 0xAC: INDEX_OP_REG(I_CMP16, SP); break; // CMPS (Indexed)
|
|
|
|
|
case 0xB3: EXT_CMP_16(CMP16, US); break; // CMPU (Extended)
|
|
|
|
|
case 0xBC: EXT_CMP_16(CMP16, SP); break; // CMPS (Extended)
|
2019-03-30 21:09:04 +00:00
|
|
|
|
|
|
|
|
default: ILLEGAL(); break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
