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MC6809: more decoding work

This commit is contained in:
alyosha-tas 2019-04-06 10:06:23 -05:00
parent b2584145d7
commit 8995e2e977
5 changed files with 336 additions and 83 deletions
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144
BizHawk.Emulation.Cores/CPUs/MC6809/Execute.cs
View File

@ -180,41 +180,41 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case 0x9A: DIRECT_MEM_4(OR8, A); break; // ORA (Direct)
case 0x9B: DIRECT_MEM_4(ADD8, A); break; // ADDA (Direct)
case 0x9C: DIR_CMP_16(CMP16, X); break; // CMPX (Direct)
case 0x9D: REG_OP(ADC8, A); break; // JSR (Direct)
case 0x9E: REG_OP(ADC8, A); break; // LDX (Direct)
case 0x9F: REG_OP(ADC8, A); break; // STX (Direct)
case 0xA0: REG_OP(AND8, A); break; // SUBA (Indexed)
case 0xA1: REG_OP(AND8, A); break; // CMPA (Indexed)
case 0xA2: REG_OP(AND8, A); break; // SBCA (Indexed)
case 0xA3: REG_OP(AND8, A); break; // SUBD (Indexed)
case 0xA4: REG_OP(AND8, A); break; // ANDA (Indexed)
case 0xA5: REG_OP(AND8, A); break; // BITA (Indexed)
case 0xA6: REG_OP(AND8, A); break; // LDA (Indexed)
case 0xA7: REG_OP(AND8, A); break; // STA (Indexed)
case 0xA8: REG_OP(XOR8, A); break; // EORA (Indexed)
case 0xA9: REG_OP(XOR8, A); break; // ADCA (Indexed)
case 0xAA: REG_OP(XOR8, A); break; // ORA (Indexed)
case 0xAB: REG_OP(XOR8, A); break; // ADDA (Indexed)
case 0xAC: REG_OP(XOR8, A); break; // CMPX (Indexed)
case 0xAD: REG_OP(XOR8, A); break; // JSR (Indexed)
case 0xAE: REG_OP(XOR8, A); break; // LDX (Indexed)
case 0xAF: REG_OP(XOR8, A); break; // STX (Indexed)
case 0xB0: REG_OP(AND8, A); break; // SUBA (Extended)
case 0xB1: REG_OP(AND8, A); break; // CMPA (Extended)
case 0xB2: REG_OP(AND8, A); break; // SBCA (Extended)
case 0xB3: REG_OP(AND8, A); break; // SUBD (Extended)
case 0xB4: REG_OP(AND8, A); break; // ANDA (Extended)
case 0xB5: REG_OP(AND8, A); break; // BITA (Extended)
case 0xB6: REG_OP(AND8, A); break; // LDA (Extended)
case 0xB7: REG_OP(AND8, A); break; // STA (Extended)
case 0xB8: REG_OP(XOR8, A); break; // EORA (Extended)
case 0xB9: REG_OP(XOR8, A); break; // ADCA (Extended)
case 0xBA: REG_OP(XOR8, A); break; // ORA (Extended)
case 0xBB: REG_OP(XOR8, A); break; // ADDA (Extended)
case 0xBC: REG_OP(XOR8, A); break; // CMPX (Extended)
case 0xBD: REG_OP(XOR8, A); break; // JSR (Extended)
case 0xBE: REG_OP(XOR8, A); break; // LDX (Extended)
case 0xBF: REG_OP(XOR8, A); break; // STX (Extended)
case 0x9D: REG_OP(ADC8, A); break; // JSR (Direct)
case 0x9E: DIR_OP_LD_16(X); break; // LDX (Direct)
case 0x9F: DIR_OP_ST_16(X); break; // STX (Direct)
case 0xA0: INDEX_OP_REG(I_SUB, A); break; // SUBA (Indexed)
case 0xA1: INDEX_OP_REG(I_CMP, A); break; // CMPA (Indexed)
case 0xA2: INDEX_OP_REG(I_SBC, A); break; // SBCA (Indexed)
case 0xA3: INDEX_OP_REG(I_SUBD, D); break; // SUBD (Indexed)
case 0xA4: INDEX_OP_REG(I_AND, A); break; // ANDA (Indexed)
case 0xA5: INDEX_OP_REG(I_BIT, A); break; // BITA (Indexed)
case 0xA6: INDEX_OP_REG(I_LD, A); break; // LDA (Indexed)
case 0xA7: INDEX_OP_REG(I_ST, A); break; // STA (Indexed)
case 0xA8: INDEX_OP_REG(I_XOR, A); break; // EORA (Indexed)
case 0xA9: INDEX_OP_REG(I_ADC, A); break; // ADCA (Indexed)
case 0xAA: INDEX_OP_REG(I_OR, A); break; // ORA (Indexed)
case 0xAB: INDEX_OP_REG(I_ADD, A); break; // ADDA (Indexed)
case 0xAC: INDEX_OP_REG(I_CMP16, X); break; // CMPX (Indexed)
case 0xAD: INDEX_OP(I_JSR); break; // JSR (Indexed)
case 0xAE: INDEX_OP_REG(I_LD16, X); break; // LDX (Indexed)
case 0xAF: INDEX_OP_REG(I_ST16, X); break; // STX (Indexed)
case 0xB0: EXT_REG(SUB8, A); break; // SUBA (Extended)
case 0xB1: EXT_REG(CMP8, A); break; // CMPA (Extended)
case 0xB2: EXT_REG(SBC8, A); break; // SBCA (Extended)
case 0xB3: EXT_OP_D(SUB16, D); break; // SUBD (Extended)
case 0xB4: EXT_REG(AND8, A); break; // ANDA (Extended)
case 0xB5: EXT_REG(BIT, A); break; // BITA (Extended)
case 0xB6: EXT_REG(TR, A); break; // LDA (Extended)
case 0xB7: EXT_ST(A); break; // STA (Extended)
case 0xB8: EXT_REG(XOR8, A); break; // EORA (Extended)
case 0xB9: EXT_REG(ADC8, A); break; // ADCA (Extended)
case 0xBA: EXT_REG(OR8, A); break; // ORA (Extended)
case 0xBB: EXT_REG(ADD8, A); break; // ADDA (Extended)
case 0xBC: EXT_CMP_16(CMP16, X); break; // CMPX (Extended)
case 0xBD: JSR_EXT(); break; // JSR (Extended)
case 0xBE: EXT_OP_LD_16(X); break; // LDX (Extended)
case 0xBF: EXT_OP_ST_16(X); break; // STX (Extended)
case 0xC0: REG_OP_IMD(SUB8, B); break; // SUBB (Immediate)
case 0xC1: REG_OP_IMD(CMP8, B); break; // CMPB (Immediate)
case 0xC2: REG_OP_IMD(SBC8, B); break; // SBCB (Immediate)
@ -227,7 +227,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case 0xC9: REG_OP_IMD(ADC8, B); break; // ADCB (Immediate)
case 0xCA: REG_OP_IMD(OR8, B); break; // ORB (Immediate)
case 0xCB: REG_OP_IMD(ADD8, B); break; // ADDB (Immediate)
case 0xCC: REG_OP_LD_16D(D); break; // LDD (Immediate)
case 0xCC: REG_OP_LD_16D(); break; // LDD (Immediate)
case 0xCD: ILLEGAL(); break; // ILLEGAL
case 0xCE: REG_OP_LD_16(US); break; // LDU (Immediate)
case 0xCF: ILLEGAL(); break; // ILLEGAL
@ -243,42 +243,42 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case 0xD9: DIRECT_MEM_4(ADC8, B); break; // ADCB (Direct)
case 0xDA: DIRECT_MEM_4(OR8, B); break; // ORB (Direct)
case 0xDB: DIRECT_MEM_4(ADD8, B); break; // ADDB (Direct)
case 0xDC: DIRECT_MEM_4(ADC8, B); break; // LDD (Direct)
case 0xDD: DIRECT_MEM_4(ADC8, B); break; // STD (Direct)
case 0xDE: REG_OP(ADC8, B); break; // LDU (Direct)
case 0xDF: REG_OP(ADC8, B); break; // STU (Direct)
case 0xE0: REG_OP(AND8, B); break; // SUBB (Indexed)
case 0xE1: REG_OP(AND8, B); break; // CMPB (Indexed)
case 0xE2: REG_OP(AND8, B); break; // SBCB (Indexed)
case 0xE3: REG_OP(AND8, B); break; // ADDD (Indexed)
case 0xE4: REG_OP(AND8, B); break; // ANDB (Indexed)
case 0xE5: REG_OP(AND8, B); break; // BITB (Indexed)
case 0xE6: REG_OP(AND8, B); break; // LDB (Indexed)
case 0xE7: REG_OP(AND8, B); break; // STB (Indexed)
case 0xE8: REG_OP(XOR8, B); break; // EORB (Indexed)
case 0xE9: REG_OP(XOR8, B); break; // ADCB (Indexed)
case 0xEA: REG_OP(XOR8, B); break; // ORB (Indexed)
case 0xEB: REG_OP(XOR8, B); break; // ADDB (Indexed)
case 0xEC: REG_OP(XOR8, B); break; // LDD (Indexed)
case 0xED: REG_OP(XOR8, B); break; // STD (Indexed)
case 0xEE: REG_OP(XOR8, B); break; // LDU (Indexed)
case 0xEF: REG_OP(XOR8, B); break; // STU (Indexed)
case 0xF0: REG_OP(AND8, B); break; // SUBB (Extended)
case 0xF1: REG_OP(AND8, B); break; // CMPB (Extended)
case 0xF2: REG_OP(AND8, B); break; // SBCB (Extended)
case 0xF3: REG_OP(AND8, B); break; // ADDD (Extended)
case 0xF4: REG_OP(AND8, B); break; // ANDB (Extended)
case 0xF5: REG_OP(AND8, B); break; // BITB (Extended)
case 0xF6: REG_OP(AND8, B); break; // LDB (Extended)
case 0xF7: REG_OP(AND8, B); break; // STB (Extended)
case 0xF8: REG_OP(XOR8, B); break; // EORB (Extended)
case 0xF9: REG_OP(XOR8, B); break; // ADCB (Extended)
case 0xFA: REG_OP(XOR8, B); break; // ORB (Extended)
case 0xFB: REG_OP(XOR8, B); break; // ADDB (Extended)
case 0xFC: REG_OP(XOR8, B); break; // LDD (Extended)
case 0xFD: REG_OP(XOR8, B); break; // STD (Extended)
case 0xFE: REG_OP(XOR8, B); break; // LDU (Extended)
case 0xFF: REG_OP(XOR8, B); break; // STU (Extended)
case 0xDC: DIR_OP_LD_16D(); break; // LDD (Direct)
case 0xDD: DIR_OP_ST_16D(); break; // STD (Direct)
case 0xDE: DIR_OP_LD_16(US); break; // LDU (Direct)
case 0xDF: DIR_OP_ST_16(US); break; // STU (Direct)
case 0xE0: INDEX_OP_REG(I_SUB, B); break; // SUBB (Indexed)
case 0xE1: INDEX_OP_REG(I_CMP, B); break; // CMPB (Indexed)
case 0xE2: INDEX_OP_REG(I_SBC, B); break; // SBCB (Indexed)
case 0xE3: INDEX_OP_REG(I_ADDD, D); break; // ADDD (Indexed)
case 0xE4: INDEX_OP_REG(I_AND, B); break; // ANDB (Indexed)
case 0xE5: INDEX_OP_REG(I_BIT, B); break; // BITB (Indexed)
case 0xE6: INDEX_OP_REG(I_LD, B); break; // LDB (Indexed)
case 0xE7: INDEX_OP_REG(I_ST, B); break; // STB (Indexed)
case 0xE8: INDEX_OP_REG(I_XOR, B); break; // EORB (Indexed)
case 0xE9: INDEX_OP_REG(I_ADC, B); break; // ADCB (Indexed)
case 0xEA: INDEX_OP_REG(I_OR, B); break; // ORB (Indexed)
case 0xEB: INDEX_OP_REG(I_ADD, B); break; // ADDB (Indexed)
case 0xEC: INDEX_OP_REG(I_LD16D, D); break; // LDD (Indexed)
case 0xED: INDEX_OP_REG(I_ST16D, D); break; // STD (Indexed)
case 0xEE: INDEX_OP_REG(I_LD16, US); break; // LDU (Indexed)
case 0xEF: INDEX_OP_REG(I_ST16, US); break; // STU (Indexed)
case 0xF0: EXT_REG(SUB8, B); break; // SUBB (Extended)
case 0xF1: EXT_REG(CMP8, B); break; // CMPB (Extended)
case 0xF2: EXT_REG(SBC8, B); break; // SBCB (Extended)
case 0xF3: EXT_OP_D(ADD16, D); break; // ADDD (Extended)
case 0xF4: EXT_REG(AND8, B); break; // ANDB (Extended)
case 0xF5: EXT_REG(BIT, B); break; // BITB (Extended)
case 0xF6: EXT_REG(TR, B); break; // LDB (Extended)
case 0xF7: EXT_ST(B); break; // STB (Extended)
case 0xF8: EXT_REG(XOR8, B); break; // EORB (Extended)
case 0xF9: EXT_REG(ADC8, B); break; // ADCB (Extended)
case 0xFA: EXT_REG(OR8, B); break; // ORB (Extended)
case 0xFB: EXT_REG(ADD8, B); break; // ADDB (Extended)
case 0xFC: EXT_OP_LD_16D(); break; // LDD (Extended)
case 0xFD: EXT_OP_ST_16D(); break; // STD (Extended)
case 0xFE: EXT_OP_LD_16(US); break; // LDU (Extended)
case 0xFF: EXT_OP_ST_16(US); break; // STU (Extended)
}
}

114
BizHawk.Emulation.Cores/CPUs/MC6809/Indexed_Modes.cs
View File

@ -20,9 +20,29 @@ namespace BizHawk.Emulation.Common.Components.MC6809
public const ushort I_TST = 13;
public const ushort I_JMP = 14;
public const ushort I_CLR = 15;
public const ushort I_SUB = 16;
public const ushort I_CMP = 17;
public const ushort I_SBC = 18;
public const ushort I_AND = 19;
public const ushort I_BIT = 20;
public const ushort I_LD = 21;
public const ushort I_ST = 22;
public const ushort I_XOR = 23;
public const ushort I_ADC = 24;
public const ushort I_OR = 25;
public const ushort I_ADD = 26;
public const ushort I_SUBD = 27;
public const ushort I_ADDD = 28;
public const ushort I_CMP16 = 29;
public const ushort I_JSR = 30;
public const ushort I_LD16 = 31;
public const ushort I_ST16 = 32;
public const ushort I_LD16D = 33;
public const ushort I_ST16D = 34;
public ushort indexed_op;
public ushort indexed_reg;
public ushort indexed_op_reg;
public ushort temp;
@ -33,17 +53,74 @@ namespace BizHawk.Emulation.Common.Components.MC6809
PopulateCURINSTR(RD_INC_OP, ALU, PC, IDX_DCDE);
}
private void INDEX_OP_REG(ushort oper, ushort src)
{
indexed_op = oper;
indexed_op_reg = src;
PopulateCURINSTR(RD_INC_OP, ALU, PC, IDX_DCDE);
}
private void INDEX_OP_JMP()
{
PopulateCURINSTR(TR, PC, IDX_EA);
}
private void INDEX_OP_JSR()
{
PopulateCURINSTR(IDLE,
IDLE,
TR, PC, IDX_EA,
WR_DEC_LO, SP, ADDR,
WR_HI, SP, ADDR);
}
private void INDEX_OP_LEA(ushort dest)
{
PopulateCURINSTR(TR, dest, IDX_EA,
IDLE);
}
private void INDEX_OP_LD()
{
PopulateCURINSTR(IDLE,
RD_INC, ALU, IDX_EA,
RD_INC_OP, ALU2, IDX_EA, SET_ADDR, indexed_op_reg, ALU, ALU2);
}
private void INDEX_OP_ST()
{
PopulateCURINSTR(IDLE,
WR_HI_INC, IDX_EA, indexed_op_reg,
WR_DEC_LO, IDX_EA, indexed_op_reg);
}
private void INDEX_OP_LDD()
{
PopulateCURINSTR(IDLE,
RD_INC, A, IDX_EA,
RD_INC, B, IDX_EA);
}
private void INDEX_OP_STD()
{
PopulateCURINSTR(SET_ADDR, ADDR, A, A,
WR_HI_INC, IDX_EA, ADDR,
WR_DEC_LO, IDX_EA, B);
}
private void INDEX_OP_EX4(ushort oper)
{
PopulateCURINSTR(IDLE,
RD_INC_OP, ALU, IDX_EA, oper, indexed_op_reg, ALU);
}
private void INDEX_OP_EX4_ST()
{
PopulateCURINSTR(IDLE,
WR, ALU, IDX_EA, indexed_op_reg);
}
private void INDEX_OP_EX5()
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, IDX_DCDE);
@ -57,6 +134,24 @@ namespace BizHawk.Emulation.Common.Components.MC6809
WR, IDX_EA, ALU);
}
private void INDEX_OP_EX6D(ushort oper)
{
PopulateCURINSTR(IDLE,
RD_INC, ALU, IDX_EA,
RD_INC_OP, ALU2, IDX_EA, SET_ADDR, ADDR, ALU, ALU2,
oper, ADDR);
}
private void INDEX_CMP_EX6(ushort oper)
{
PopulateCURINSTR(IDLE,
RD_INC, ALU, IDX_EA,
RD_INC_OP, ALU2, IDX_EA, SET_ADDR, ADDR, ALU, ALU2,
oper, indexed_op_reg, ADDR);
}
private void INDEX_OP_EX7()
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, IDX_DCDE);
@ -310,6 +405,25 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case I_TST: INDEX_OP_EX6(TST); break; // TST
case I_JMP: INDEX_OP_JMP(); break; // JMP
case I_CLR: INDEX_OP_EX6(CLR); break; // CLR
case I_SUB: INDEX_OP_EX4(SUB8); break; // SUB A,B
case I_CMP: INDEX_OP_EX4(CMP8); break; // CMP A,B
case I_SBC: INDEX_OP_EX4(SBC8); break; // SBC A,B
case I_AND: INDEX_OP_EX4(AND8); break; // AND A,B
case I_BIT: INDEX_OP_EX4(BIT); break; // BIT A,B
case I_LD: INDEX_OP_EX4(TR); break; // LD A,B
case I_ST: INDEX_OP_EX4_ST(); break; // ST A,B
case I_XOR: INDEX_OP_EX4(XOR8); break; // XOR A,B
case I_ADC: INDEX_OP_EX4(ADC8); break; // ADC A,B
case I_OR: INDEX_OP_EX4(OR8); break; // OR A,B
case I_ADD: INDEX_OP_EX4(ADD8); break; // ADD A,B
case I_SUBD: INDEX_OP_EX6D(SUB16); break; // SUB D
case I_ADDD: INDEX_OP_EX6D(ADD16); break; // ADD D
case I_CMP16: INDEX_CMP_EX6(CMP16); break; // CMP X, Y, SP, US
case I_JSR: INDEX_OP_JSR(); break; // JSR
case I_LD16: INDEX_OP_LD(); break; // LD X, Y, SP, US
case I_ST16: INDEX_OP_ST(); break; // ST X, Y, SP, US
case I_LD16D: INDEX_OP_LDD(); break; // LD D
case I_ST16D: INDEX_OP_STD(); break; // ST D
}
}
}

7
BizHawk.Emulation.Cores/CPUs/MC6809/MC6809.cs
View File

@ -91,6 +91,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
public const ushort SUB16 = 77;
public const ushort ADD16 = 78;
public const ushort CMP16 = 79;
public const ushort WR_HI_INC = 80;
public MC6809()
{
@ -244,6 +245,9 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case CMP8:
CMP8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
case DEC16:
DEC16_Func(cur_instr[instr_pntr++]);
break;
case TR:
TR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
@ -302,6 +306,9 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case WR_HI:
Write_Hi_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
case WR_HI_INC:
Write_Hi_Inc_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
case TR:
TR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;

7
BizHawk.Emulation.Cores/CPUs/MC6809/Operations.cs
View File

@ -78,6 +78,13 @@ namespace BizHawk.Emulation.Common.Components.MC6809
WriteMemory(Regs[dest], (byte)(Regs[src] >> 8));
}
public void Write_Hi_Inc_Func(ushort dest, ushort src)
{
if (CDLCallback != null) CDLCallback(Regs[dest], eCDLogMemFlags.Write | eCDLogMemFlags.Data);
WriteMemory(Regs[dest], (byte)(Regs[src] >> 8));
Regs[dest]++;
}
public void TR_Func(ushort dest, ushort src)
{
Regs[dest] = Regs[src];

147
BizHawk.Emulation.Cores/CPUs/MC6809/Tables_Direct.cs
View File

@ -23,6 +23,11 @@ namespace BizHawk.Emulation.Common.Components.MC6809
}
private void REG_OP(ushort oper, ushort src)
{
PopulateCURINSTR(oper, src);
}
private void DIRECT_MEM(ushort oper)
{
PopulateCURINSTR(RD_INC, ALU, PC,
@ -35,15 +40,15 @@ namespace BizHawk.Emulation.Common.Components.MC6809
private void DIRECT_ST_4(ushort dest)
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
RD, ALU, ADDR,
IDLE,
WR, ADDR, dest);
}
private void DIRECT_MEM_4(ushort oper, ushort dest)
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
RD, ALU, ADDR,
oper, dest, ALU);
IDLE,
RD_INC_OP, ALU, ADDR, oper, dest, ALU);
}
private void EXT_MEM(ushort oper)
@ -56,6 +61,22 @@ namespace BizHawk.Emulation.Common.Components.MC6809
WR, ADDR, ALU);
}
private void EXT_REG(ushort oper, ushort dest)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
RD, ALU, ADDR,
oper, dest, ALU);
}
private void EXT_ST(ushort dest)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
IDLE,
WR, ADDR, dest);
}
private void REG_OP_IMD_CC(ushort oper)
{
Regs[ALU2] = Regs[CC];
@ -84,6 +105,38 @@ namespace BizHawk.Emulation.Common.Components.MC6809
oper, ADDR);
}
private void EXT_OP_D(ushort oper, ushort dest)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
RD_INC, ALU, ADDR,
RD, ALU2, ADDR,
SET_ADDR, ADDR, ALU, ALU2,
oper, ADDR);
}
private void REG_OP_LD_16D()
{
PopulateCURINSTR(RD_INC, A, PC,
RD_INC, B, PC);
}
private void DIR_OP_LD_16D()
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
IDLE,
RD_INC, A, ADDR,
RD_INC, B, ADDR);
}
private void DIR_OP_ST_16D()
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
SET_ADDR, ALU, A, A,
WR_HI_INC, ADDR, ALU,
WR, ADDR, B);
}
private void DIR_CMP_16(ushort oper, ushort dest)
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
@ -99,10 +152,66 @@ namespace BizHawk.Emulation.Common.Components.MC6809
RD_INC_OP, ALU2, PC, SET_ADDR, dest, ALU, ALU2);
}
private void REG_OP_LD_16D(ushort dest)
private void DIR_OP_LD_16(ushort dest)
{
PopulateCURINSTR(RD_INC, A, PC,
RD_INC, B, PC);
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
IDLE,
RD_INC, ALU, ADDR,
RD_INC_OP, ALU2, ADDR, SET_ADDR, dest, ALU, ALU2);
}
private void DIR_OP_ST_16(ushort src)
{
PopulateCURINSTR(RD_INC_OP, ALU, PC, SET_ADDR, ADDR, DP, ALU,
IDLE,
WR_HI_INC, ADDR, src,
WR_DEC_LO, ADDR, src);
}
private void EXT_OP_LD_16(ushort dest)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
IDLE,
RD_INC, ALU, ADDR,
RD_INC_OP, ALU2, ADDR, SET_ADDR, dest, ALU, ALU2);
}
private void EXT_OP_ST_16(ushort src)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
IDLE,
WR_HI_INC, ADDR, src,
WR_DEC_LO, ADDR, src);
}
private void EXT_OP_LD_16D()
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
IDLE,
RD_INC, A, ADDR,
RD_INC, B, ADDR);
}
private void EXT_OP_ST_16D()
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
SET_ADDR, ALU, A, A,
WR_HI_INC, ADDR, ALU,
WR, ADDR, B);
}
private void EXT_CMP_16(ushort oper, ushort dest)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC, SET_ADDR, ADDR, ALU, ALU2,
RD_INC, ALU, ADDR,
RD, ALU2, ADDR,
SET_ADDR, ADDR, ALU, ALU2,
oper, dest, ADDR);
}
private void EXG_()
@ -125,11 +234,6 @@ namespace BizHawk.Emulation.Common.Components.MC6809
IDLE);
}
private void REG_OP(ushort oper, ushort src)
{
PopulateCURINSTR(oper, src);
}
private void JMP_DIR_()
{
PopulateCURINSTR(RD_INC, ALU, PC,
@ -143,6 +247,27 @@ namespace BizHawk.Emulation.Common.Components.MC6809
SET_ADDR, PC, ALU, ALU2);
}
private void JSR_()
{
PopulateCURINSTR(RD_INC, ALU, PC,
SET_ADDR, ADDR, DP, ALU,
IDLE,
TR, PC, ADDR,
WR_DEC_LO, SP, ADDR,
WR_HI, SP, ADDR);
}
private void JSR_EXT()
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC_OP, ALU2, PC,
SET_ADDR, ADDR, ALU, ALU2,
IDLE,
TR, PC, ADDR,
WR_DEC_LO, SP, ADDR,
WR_HI, SP, ADDR);
}
private void LBR_(bool cond)
{
if (cond)