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Vectrex commit 2

This commit is contained in:
alyosha-tas 2019-03-31 08:27:51 -05:00
parent ba4ec02cb5
commit 33af0b7fee
4 changed files with 146 additions and 27 deletions
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79
BizHawk.Emulation.Cores/CPUs/MC6809/Execute.cs
View File

@ -80,11 +80,11 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case 0x36: ; break; // PSHU (Immediate)
case 0x37: ; break; // PULU (Immediate)
case 0x38: ILLEGAL(); break; // ILLEGAL
case 0x39: ; break; // RTS (Inherent)
case 0x3A: ; break; // ABX (Inherent)
case 0x3B: ; break; // RTI (Inherent)
case 0x39: RTS(); break; // RTS (Inherent)
case 0x3A: ABX_(); break; // ABX (Inherent)
case 0x3B: RTI(); break; // RTI (Inherent)
case 0x3C: ; break; // CWAI (Inherent)
case 0x3D: ; break; // MUL (Inherent)
case 0x3D: MUL_(); break; // MUL (Inherent)
case 0x3E: ILLEGAL(); break; // ILLEGAL
case 0x3F: ; break; // SWI (Inherent)
case 0x40: REG_OP(NEG, A); break; // NEGA (Inherent)
@ -135,22 +135,22 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case 0x6D: REG_OP(TR, A); break; // TST (Indexed)
case 0x6E: REG_OP(TR, A); break; // JMP (Indexed)
case 0x6F: REG_OP(TR, A); break; // CLR (Indexed)
case 0x70: REG_OP(TR, A); break; // NEG (Extended)
case 0x70: EXT_MEM(NEG); break; // NEG (Extended)
case 0x71: ILLEGAL(); break; // ILLEGAL
case 0x72: ILLEGAL(); break; // ILLEGAL
case 0x73: REG_OP(TR, A); break; // COM (Extended)
case 0x74: REG_OP(TR, A); break; // LSR (Extended)
case 0x73: EXT_MEM(COM); break; // COM (Extended)
case 0x74: EXT_MEM(LSR); break; // LSR (Extended)
case 0x75: ILLEGAL(); break; // ILLEGAL
case 0x76: REG_OP(TR, A); break; // ROR (Extended)
case 0x77: REG_OP(TR, A); break; // ASR (Extended)
case 0x78: REG_OP(TR, A); break; // ASL , LSL (Extended)
case 0x79: REG_OP(TR, A); break; // ROL (Extended)
case 0x7A: REG_OP(TR, A); break; // DEC (Extended)
case 0x76: EXT_MEM(ROR); break; // ROR (Extended)
case 0x77: EXT_MEM(ASR); break; // ASR (Extended)
case 0x78: EXT_MEM(ASL); break; // ASL , LSL (Extended)
case 0x79: EXT_MEM(ROL); break; // ROL (Extended)
case 0x7A: EXT_MEM(DEC8); break; // DEC (Extended)
case 0x7B: ILLEGAL(); break; // ILLEGAL
case 0x7C: REG_OP(TR, A); break; // INC (Extended)
case 0x7D: REG_OP(TR, A); break; // TST (Extended)
case 0x7E: REG_OP(TR, A); break; // JMP (Extended)
case 0x7F: REG_OP(TR, A); break; // CLR (Extended)
case 0x7C: EXT_MEM(INC8); break; // INC (Extended)
case 0x7D: EXT_MEM(TST); break; // TST (Extended)
case 0x7E: JMP_EXT_(); break; // JMP (Extended)
case 0x7F: EXT_MEM(CLR); break; // CLR (Extended)
case 0x80: REG_OP(ADD8, A); break; // SUBA (Immediate)
case 0x81: REG_OP(ADD8, A); break; // CMPA (Immediate)
case 0x82: REG_OP(ADD8, A); break; // SBCA (Immediate)
@ -286,6 +286,44 @@ namespace BizHawk.Emulation.Common.Components.MC6809
{
switch (opcode)
{
case 0x21: REG_OP(XOR8, B); break; // LBRN (Relative)
case 0x22: REG_OP(XOR8, B); break; // LBHI (Relative)
case 0x23: REG_OP(XOR8, B); break; // LBLS (Relative)
case 0x24: REG_OP(XOR8, B); break; // LBHS , LBCC (Relative)
case 0x25: REG_OP(XOR8, B); break; // LBCS , LBLO (Relative)
case 0x26: REG_OP(XOR8, B); break; // LBNE (Relative)
case 0x27: REG_OP(XOR8, B); break; // LBEQ (Relative)
case 0x28: REG_OP(XOR8, B); break; // LBVC (Relative)
case 0x29: REG_OP(XOR8, B); break; // LBVS (Relative)
case 0x2A: REG_OP(XOR8, B); break; // LBPL (Relative)
case 0x2B: REG_OP(XOR8, B); break; // LBMI (Relative)
case 0x2C: REG_OP(XOR8, B); break; // LBGE (Relative)
case 0x2D: REG_OP(XOR8, B); break; // LBLT (Relative)
case 0x2E: REG_OP(XOR8, B); break; // LBGT (Relative)
case 0x2F: REG_OP(XOR8, B); break; // LBLE (Relative)
case 0x3F: REG_OP(XOR8, B); break; // SWI2 (Inherent)
case 0x83: REG_OP(XOR8, B); break; // CMPD (Immediate)
case 0x8C: REG_OP(XOR8, B); break; // CMPY (Immediate)
case 0x8E: REG_OP(XOR8, B); break; // LDY (Immediate)
case 0x93: REG_OP(XOR8, B); break; // CMPD (Direct)
case 0x9C: REG_OP(XOR8, B); break; // CMPY (Direct)
case 0x9E: REG_OP(XOR8, B); break; // LDY (Direct)
case 0x9F: REG_OP(XOR8, B); break; // STY (Direct)
case 0xA3: REG_OP(XOR8, B); break; // CMPD (Indexed)
case 0xAC: REG_OP(XOR8, B); break; // CMPY (Indexed)
case 0xAE: REG_OP(XOR8, B); break; // LDY (Indexed)
case 0xAF: REG_OP(XOR8, B); break; // STY (Indexed)
case 0xB3: REG_OP(XOR8, B); break; // CMPD (Extended)
case 0xBC: REG_OP(XOR8, B); break; // CMPY (Extended)
case 0xBE: REG_OP(XOR8, B); break; // LDY (Extended)
case 0xBF: REG_OP(XOR8, B); break; // STY (Extended)
case 0xCE: REG_OP(XOR8, B); break; // LDS (Immediate)
case 0xDE: REG_OP(XOR8, B); break; // LDS (Direct)
case 0xDF: REG_OP(XOR8, B); break; // STS (Direct)
case 0xEE: REG_OP(XOR8, B); break; // LDS (Indexed)
case 0xEF: REG_OP(XOR8, B); break; // STS (Indexed)
case 0xFE: REG_OP(XOR8, B); break; // LDS (Extended)
case 0xFF: REG_OP(XOR8, B); break; // STS (Extended)
default: ILLEGAL(); break;
}
@ -295,6 +333,15 @@ namespace BizHawk.Emulation.Common.Components.MC6809
{
switch (opcode)
{
case 0x3F: REG_OP(XOR8, B); break; // SWI3 (Inherent)
case 0x83: REG_OP(XOR8, B); break; // CMPU (Immediate)
case 0x8C: REG_OP(XOR8, B); break; // CMPS (Immediate)
case 0x93: REG_OP(XOR8, B); break; // CMPU (Direct)
case 0x9C: REG_OP(XOR8, B); break; // CMPS (Direct)
case 0xA3: REG_OP(XOR8, B); break; // CMPU (Indexed)
case 0xAC: REG_OP(XOR8, B); break; // CMPS (Indexed)
case 0xB3: REG_OP(XOR8, B); break; // CMPU (Extended)
case 0xBC: REG_OP(XOR8, B); break; // CMPS (Extended)
default: ILLEGAL(); break;
}

18
BizHawk.Emulation.Cores/CPUs/MC6809/MC6809.cs
View File

@ -71,6 +71,9 @@ namespace BizHawk.Emulation.Common.Components.MC6809
public const ushort WR_DEC_LO = 57;
public const ushort WR_HI = 58;
public const ushort ADD8BR = 59;
public const ushort ABX = 60;
public const ushort MUL = 61;
public const ushort JPE = 62;
public MC6809()
{
@ -206,6 +209,12 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case SUB8:
SUB8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
case SET_ADDR:
Regs[cur_instr[instr_pntr++]] = (ushort)((Regs[cur_instr[instr_pntr++]] << 8) | Regs[cur_instr[instr_pntr++]]);
break;
case JPE:
if (!FlagE) { instr_pntr = 35; };
break;
}
break;
case WR:
@ -241,6 +250,12 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case SEX:
SEX_Func(cur_instr[instr_pntr++]);
break;
case ABX:
Regs[X] += Regs[B];
break;
case MUL:
Mul_Func();
break;
case ADD16BR:
ADD16BR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
@ -414,7 +429,8 @@ namespace BizHawk.Emulation.Common.Components.MC6809
private void PopulateCURINSTR(ushort d0 = 0, ushort d1 = 0, ushort d2 = 0, ushort d3 = 0, ushort d4 = 0, ushort d5 = 0, ushort d6 = 0, ushort d7 = 0, ushort d8 = 0,
ushort d9 = 0, ushort d10 = 0, ushort d11 = 0, ushort d12 = 0, ushort d13 = 0, ushort d14 = 0, ushort d15 = 0, ushort d16 = 0, ushort d17 = 0, ushort d18 = 0,
ushort d19 = 0, ushort d20 = 0, ushort d21 = 0, ushort d22 = 0, ushort d23 = 0, ushort d24 = 0, ushort d25 = 0, ushort d26 = 0, ushort d27 = 0, ushort d28 = 0,
ushort d29 = 0, ushort d30 = 0, ushort d31 = 0, ushort d32 = 0, ushort d33 = 0, ushort d34 = 0, ushort d35 = 0, ushort d36 = 0, ushort d37 = 0)
ushort d29 = 0, ushort d30 = 0, ushort d31 = 0, ushort d32 = 0, ushort d33 = 0, ushort d34 = 0, ushort d35 = 0, ushort d36 = 0, ushort d37 = 0, ushort d38 = 0,
ushort d39 = 0, ushort d40 = 0, ushort d41 = 0, ushort d42 = 0, ushort d43 = 0, ushort d44 = 0, ushort d45 = 0, ushort d46 = 0, ushort d47 = 0, ushort d48 = 0)
{
cur_instr[0] = d0; cur_instr[1] = d1; cur_instr[2] = d2;
cur_instr[3] = d3; cur_instr[4] = d4; cur_instr[5] = d5;

8
BizHawk.Emulation.Cores/CPUs/MC6809/Operations.cs
View File

@ -106,6 +106,14 @@ namespace BizHawk.Emulation.Common.Components.MC6809
Regs[dest] = (ushort)(Regs[dest] + (short)Regs[src]);
}
public void Mul_Func()
{
Regs[ALU] = (ushort)(Regs[A] * Regs[B]);
D = Regs[ALU];
FlagC = Regs[B] > 127;
FlagZ = D == 0;
}
public void ADD8_Func(ushort dest, ushort src)
{
int Reg16_d = Regs[dest];

68
BizHawk.Emulation.Cores/CPUs/MC6809/Tables_Direct.cs
View File

@ -31,6 +31,16 @@ namespace BizHawk.Emulation.Common.Components.MC6809
WR, ADDR);
}
private void EXT_MEM(ushort oper)
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC, ALU2, PC,
SET_ADDR, ADDR, ALU, ALU2,
RD, ADDR,
oper, ALU,
WR, ADDR);
}
private void REG_OP_IMD_CC(ushort oper)
{
Regs[ALU2] = Regs[CC];
@ -69,6 +79,13 @@ namespace BizHawk.Emulation.Common.Components.MC6809
SET_ADDR, PC, DP, ALU);
}
private void JMP_EXT_()
{
PopulateCURINSTR(RD_INC, ALU, PC,
RD_INC, ALU2, PC,
SET_ADDR, PC, ALU, ALU2);
}
private void LBR_(bool cond)
{
if (cond)
@ -124,17 +141,48 @@ namespace BizHawk.Emulation.Common.Components.MC6809
PopulateCURINSTR(OP_PG_3);
}
private void INC_16(ushort src_l, ushort src_h)
private void ABX_()
{
cur_instr = new ushort[]
{IDLE,
IDLE,
IDLE,
INC16, src_l, src_h,
IDLE,
IDLE,
HALT_CHK,
OP };
PopulateCURINSTR(ABX,
IDLE);
}
private void MUL_()
{
PopulateCURINSTR(MUL,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
private void RTS()
{
PopulateCURINSTR(IDLE,
RD_INC, ALU, SP,
RD_INC, ALU2, SP,
SET_ADDR, PC, ALU, ALU2);
}
private void RTI()
{
PopulateCURINSTR(IDLE,
RD_INC_OP, CC, SP, JPE,
RD_INC, A, SP,
RD_INC, B, SP,
RD_INC, DP, SP,
RD_INC, ALU, SP,
RD_INC_OP, ALU2, SP, SET_ADDR, X, ALU, ALU2,
RD_INC, ALU, SP,
RD_INC_OP, ALU2, SP, SET_ADDR, Y, ALU, ALU2,
RD_INC, ALU, SP,
RD_INC_OP, ALU2, SP, SET_ADDR, US, ALU, ALU2,
SET_ADDR, PC, ALU2, ALU);
}