ShuriZma
/
xenia
mirror of https://github.com/xenia-project/xenia.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,479 Commits 10 Branches 0 Tags 85 MiB
Commit Graph

3479 Commits

Author SHA1 Message Date
Dr. Chat 008167fa66 VK: Enable full rotation / Set render_state to nullptr on failure / Fix format info in texture resolves 2016-05-25 13:49:36 -05:00
Dr. Chat a187a4931a Whoops - fix setting the wrong host base for some graphics allocations. 2016-05-25 13:14:03 -05:00
Dr. Chat 9d1e66ab16 Don't write to color targets in depth-only mode. 2016-05-24 21:58:02 -05:00
Dr. Chat ad83a1994d VK: Remove alphaToOne feature requirement 2016-05-24 12:53:25 -05:00
Dr. Chat 5f764730ae Vulkan CP: Override frame traces if renderdoc is attached 2016-05-23 13:16:13 -05:00
Dr. Chat 729152a58b VK: Enable independentBlend feature 2016-05-23 09:59:37 -05:00
Dr. Chat 6e21d88250 Fixup circular buffers for full rotation 2016-05-23 09:58:46 -05:00
Dr. Chat c6e905db2f Fix a memory leak in fenced pools. 2016-05-22 22:14:45 -05:00
Dr. Chat 7004f83665 CP: Don't check for shader validity here 
Fix a lousy typo in PrepareTextureSet
 2016-05-22 20:08:35 -05:00
Dr. Chat bd27835a3d Pipeline Cache: Translate shaders when program cntl register is available 2016-05-22 20:03:13 -05:00
Dr. Chat d1b4d61b52 SPIR-V: Use the register count from the program control register 
Workaround for broken OpBitFieldUExtract on NVIDIA drivers
kRcpc/kRcpf/kRsqc/kRsqf
Fix broken ps_ usage
 2016-05-22 20:01:42 -05:00
Dr. Chat d94ff6eb25 Shaders: Track the register count from the program control register (if available) 2016-05-22 19:58:50 -05:00
Dr. Chat 1faf5a813a Fix ALU scalar swizzles (Possibly) 2016-05-22 19:57:05 -05:00
Dr. Chat b025790207 Disable Vulkan native MSAA by default for now. 2016-05-17 05:58:52 -05:00
Dr. Chat 44284a780c SPIR-V: Misc. IR utility functions 2016-05-15 14:27:44 -05:00
Dr. Chat b9a40d1a00 Use Vulkan as the default graphics backend. 2016-05-15 12:08:29 -05:00
Dr. Chat 2bb52ef86b SPIR-V: WIP shader compiler / optimizations / alpha test implementation 2016-05-15 12:01:38 -05:00
Dr. Chat c06a7cdf81 BaseFencedPool::has_open_batch (and other uncommitted changes) 2016-05-07 19:17:56 -05:00
Dr. Chat 79f1193130 Vulkan CP: Fix calculating an invalid copy destination base address when sizeof(texel) != 4 2016-05-06 00:12:47 -05:00
Dr. Chat 7c5042add7 Vulkan CP: Add in separate swap-chain images 
Some other changes I can't remember
 2016-05-03 14:12:05 -05:00
Dr. Chat f2af28c322 TextureCache: Fix up some synchronization flaws (deleting in-use textures/etc) 
Fix texture binding IDs not matching fetch instruction IDs.
Fix some bad texture format matching.
Add access watches
 2016-05-03 14:10:15 -05:00
Dr. Chat 8e8df2e778 PipelineCache: Support shader disasm dumps for nvidia cards. 
Fix MSAA 2X multiplier.
 2016-05-03 14:07:20 -05:00
Dr. Chat d18c99aab6 RenderCache: Account for MSAA when calculating tile sizes. 
Add a new flag to enable native MSAA (this does not work properly at the moment)
 2016-05-03 14:05:34 -05:00
Dr. Chat aa038fbf23 Skip the wrapping packet end after parsing IB end (to avoid false draws appearing) 2016-05-01 15:48:31 -05:00
Dr. Chat 065f777e67 Merge branch 'vulkan' of github.com:benvanik/xenia into spv_translator 2016-05-01 11:25:16 -05:00
Dr. Chat cbccc785cc TraceViewer: Build a tree of all command buffers and display that instead of a flat list. 2016-05-01 10:15:33 -05:00
Dr. Chat 6101b70641 Fix the Vulkan immediate drawer not drawing lines. 2016-04-29 13:09:39 -05:00
Dr. Chat 9b2e2a7275 SPIR-V: Hack in OpSelectionMerge as hints to NVidia's shader compiler (TODO: Make a Shader Compiler) 2016-04-13 23:17:03 -05:00
Dr. Chat 2bd603bf18 CircularBuffer: use std::list for allocations instead of a vector. 2016-04-09 21:40:18 -05:00
Dr. Chat 4811ebc2ce BufferCache: Use a CircularBuffer as the transient buffer. 2016-04-09 21:27:32 -05:00
Dr. Chat b7f2c93d73 SPIR-V: Batch predicated instructions together into a single block. 
Add Post-Translation validation.
Fix a couple of type-related typos.
 2016-04-09 21:03:44 -05:00
Dr. Chat a1c9540063 SPIR-V Validator util class 2016-04-09 18:35:00 -05:00
Dr. Chat 3726064af5 Can't use CmdCopyBufferToImage or vice versa for depth and stencil. 2016-04-01 22:03:29 -05:00
Dr. Chat f9a634ad25 CircularBuffer remove Discard functionality and allow rotation 2016-04-01 21:53:46 -05:00
Dr. Chat 50f72b4e42 Enable native MSAA 
Copy back EDRAM buffers in order by base offset.
 2016-04-01 21:52:39 -05:00
Dr. Chat 2eca3ce9e6 Texture uploads/basic formats 
Fixed swizzle one/zero mismatch
Sampler setup
Remove samplers from the descriptor set layout
 2016-04-01 21:51:17 -05:00
Dr. Chat 1ea72c5e06 FencedPool::CancelBatch 2016-04-01 21:49:58 -05:00
Dr. Chat 44cffab389 SPIR-V Max4 2016-03-25 18:23:45 -05:00
Dr. Chat fc1bd0f379 Fix texture uploads 2016-03-25 17:29:39 -05:00
Dr. Chat 692d666d57 Wipe the buffer cache in ClearCache for now. 2016-03-25 16:50:06 -05:00
Dr. Chat 0e44cda961 Update the rectangle list shader 2016-03-25 16:49:41 -05:00
Dr. Chat d7599c817f Formatting. 2016-03-25 16:44:25 -05:00
Dr. Chat a5a31cf123 VulkanShader::Prepare - return false if vkCreateShaderModule failed. 2016-03-25 16:37:24 -05:00
Dr. Chat 2bb40c122d Vulkan util Fence class 2016-03-25 16:36:21 -05:00
Dr. Chat f75e5fec24 CP: Use a single command buffer for every frame, reuse render passes/pipelines if not dirty 
Hook up resolves and swaps
 2016-03-25 16:35:34 -05:00
Dr. Chat 1e1da1eb6c PipelineCache::ConfigurePipeline - Inform the caller if the pipeline is dirty or they can reuse the previously bound pipeline. 
Make SetDynamicState public.
 2016-03-25 16:34:14 -05:00
Dr. Chat b2457d7e72 Basic texture uploads/address lookups/etc 
Freeing of descriptor sets when the GPU is finished with them.
 2016-03-25 16:32:29 -05:00
Dr. Chat 0e41774e36 RenderCache::dirty() - used to tell if we need to begin a new pass 
Round all pixel pitch/heights up before dividing.
 2016-03-25 16:31:12 -05:00
Dr. Chat 181b2af5a4 Vulkan Circular Buffer 2016-03-25 13:49:07 -05:00
Dr. Chat e72e283e79 Primitive type makes rasterization state dirty too! 2016-03-23 16:20:06 -05:00