Commit Graph

6437 Commits

Author SHA1 Message Date
chss95cs@gmail.com 968f656d96 Add separate VMX/fpu mxcsr
Add support for constant operands for most fpu instructions
Remove constant folding for most fpu cpde
half float
2022-07-31 08:56:36 -07:00
Gliniak 5d1b641197 [Emulator] Added possiblity to install multiple packages at once 2022-07-30 15:52:41 +02:00
Gliniak 79ffbe3971 Merge branch 'importContent' of https://github.com/Gliniak/xenia.git into canary_experimental 2022-07-30 12:44:24 +02:00
Gliniak 0e3403d6da Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-30 12:42:51 +02:00
Gliniak 433a8a8a5e [Emulator] Added option for content installation 2022-07-30 12:41:26 +02:00
Triang3l 7595cdb52b [Vulkan] Non-GS point sprites + minor SPIR-V fixes 2022-07-27 17:14:28 +03:00
Triang3l ff7ef05063 [SPIR-V] Clamp cube face using NClamp, not NMax/FMin 2022-07-26 17:08:12 +03:00
Triang3l 66c995f3aa [SPIR-V] Saturate point sprite coordinates 2022-07-26 17:04:22 +03:00
Triang3l 8fb5da18ea [Vulkan] Add forgotten fullDrawIndexUint32 check 2022-07-26 16:24:14 +03:00
Triang3l 9fa41c27bc [Vulkan] Point sprite geometry shader 2022-07-26 16:01:20 +03:00
Gliniak 0c3019981c [Video] Added option to set internal output resolution 2022-07-26 11:25:03 +02:00
Gliniak 76806e08c5 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-26 10:22:38 +02:00
Triang3l f248e23079 [DXBC] Skip backface check in point PsParamGen 2022-07-25 21:48:25 +03:00
Triang3l 77e85ecaa4 [Vulkan] 32-bit index fetch without fullDrawIndexUint32 2022-07-25 16:53:12 +03:00
Gliniak 061000af01 [Base] Changed size of bitstream accessed data (Risky)
This prevents crashing in situation when buffer_ + offset_bytes is
at the end of allocated memory range and can go into unallocated space
2022-07-25 10:52:21 +02:00
Gliniak 364137ef5f [XAM] Send UI On notification on start of XamShowSigninUI 2022-07-25 10:50:32 +02:00
Gliniak 6730ffb7d3 Merge branch 'canary_experimental' of https://github.com/xenia-canary/xenia-canary into canary_experimental 2022-07-24 17:58:48 +02:00
Gliniak 6e501fbd61 [XAM] Set license mask for DLCs (Thanks Beeanyew) 2022-07-24 17:58:00 +02:00
Gliniak 98c2cb636f Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-24 17:38:08 +02:00
Triang3l 37579d3bf0 [GPU] Treat non-adaptive-tessellated patches as 1-control-point 2022-07-24 17:38:26 +03:00
chss95cs@gmail.com 33a6cfc0a7 Add special cases to DOT_PRODUCT_3/4 that detect whether they're calculating lengthsquared
Add alternate path to DOT_PRODUCT_3/4 for use_fast_dot_product that skips all the status register stuff and just remaps inf to qnan
Add OPCODE_TO_SINGLE to replace the CONVERT_F32_F64 - CONVERT_F64_F32 sequence we used to emit with the idea that a backend could implement a more correct rounding behavior if possible on its arch
Remove some impossible sequences like MUL_HI_I8/I16, MUL_ADD_F32, DIV_V128. These instructions have no equivalent in PPC. Many other instructions are unused/dead code and should be removed to make the x64 backend a better reference for future ones
Add backend_flags to Instr. Basically, flags field that a backend can use for whatever it wants when generating code.
Add backend instr flag to x64 that tells it to not generate code for an instruction. this allows sequences to consume subsequent instructions
Generate actual x64 code for VSL instruction instead of using callnativesafe
Detect repeated COMPARE instructions w/ identical operands and reuse the results in FLAGS if so. this eliminates a ton of garbage compare/set instructions.
If a COMPARE instructions destination is stored to context with no intervening instruction and no additional uses besides the store, do setx [ctx address]
Detect prefetchw and use it in CACHE_CONTROL if prefetch for write is requested instead of doing prefetch to all cache levels
Fixed an accident in an earlier commit by me, VECTOR_DENORMFLUSH was not being emitted at all, so denormal inputs to MUL_ADD_V128 were not becoming zero and outputs from DOT_PRODUCT_X were not either. I believe this introduced a bug into RDR where a wagon wouldnt spawn? (https://discord.com/channels/308194948048486401/308207592482668545/1000443975817252874)
Compute fresx in double precision using RECIP_F64 and then round to single instead of doing (double)(1.0f / (float)value), matching original behavior better
Refactor some of ppc_emit_fpu, much of the InstrEmit function are identical except for whether they round to single or not
Added "tail emitters" to X64Emitter. These are callbacks that get invoked with their label and the X64Emitter after the epilog code. This allows us to move cold code out of the critical path and in the future place constant pools near functions
guest_to_host_thunk/host_to_guest_thunk now gets directly rel32 called, instead of doing a mov
Add X64BackendContext structure, represents data before the start of the PPCContext
Instead of doing branchless sequence, do a compare and jump to tail emitted code for address translation. This makes converting addresses a 3 uop affair in most cases.
Do qnan move for dot product in a tail emitter
Detect whether EFLAGS bits are independent variables for the current cpu (not really detecting it ehe, just checking if zen) and if so generate inc/dec for add/sub 1
Detect whether low 32 bits of membase are 0. If they are then we can use membasereg.cvt32() in place of immediate 0 in many places, particularly in stores
Detect LOAD MODIFY STORE pattern for context variables (currently only done for 64 bit ones) and turn them into modify [context ptr]. This is done for add, sub, and, or, xor, not, neg
Tail emit error handling for TRAP opcodes
Stub out unused trap opcodes like TRAP_TRUE_I32, TRAP_TRUE_I64, TRAP_TRUE_I16 (the call_true/return_true opcodes for these types are also probably unused)
Remove BackpropTruncations. It was poorly written and causes crashes on the game Viva pinata (https://discord.com/channels/308194948048486401/701111856600711208/1000249460451983420)
2022-07-23 12:10:07 -07:00
Gliniak 1fcac00924 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-23 13:26:31 +02:00
Triang3l 3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Gliniak 0c782ade8e Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-21 18:52:33 +02:00
Triang3l 6ff312afb1 [DXBC] Update PsParamGen comment [ci skip] 2022-07-21 12:42:06 +03:00
Triang3l 1a95bef8b3 [GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
2022-07-21 12:32:28 +03:00
Gliniak 0f60e23208 [Kernel] Removed input change notifications from initial notify list 2022-07-19 10:46:36 +02:00
Gliniak bc315d21e0 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-19 10:45:14 +02:00
Triang3l 0a94b86cb8 [GPU] Remove orphaned GetPresentArea declaration [ci skip] 2022-07-18 21:02:34 +03:00
Gliniak 57b514ea6a Removed (again) unnecessary include 2022-07-18 09:40:45 +02:00
Radosław Gliński 3757580f45
Merge pull request #52 from chrisps/canary_experimental
Fix previous batch of CPU changes
2022-07-18 09:20:35 +02:00
Gliniak fd78ab4dfc [Patcher] Allow loading patches from non-utf8 paths 2022-07-18 08:46:04 +02:00
chss95cs@gmail.com 11817f0a3b vshufps accident broke things, this fixes 2022-07-17 14:44:09 -07:00
Gliniak 6e1e62378f Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-17 21:27:52 +02:00
Triang3l 14fdf4b270 [GPU] Up to 7x7 resolution scaling 2022-07-17 20:41:50 +03:00
chss95cs@gmail.com 3717167bbe Preload ThreeFloatMask in DOT_PRODUCT_3
Use shuffle_ps instead of broadcastss, broadcastss is slower on many intel and amd processors and encodes to the same number of bytes as shuffle_ps
Detect and optimize away PERMUTE with a zero src2 and src3 in constant_propagation_pass instead of in the x64 sequence
For constant PERMUTE, do the Xor/And prior to LoadConstantXmm instead of in the generated code
Simplified code for PERMUTE
Added simplification rule that detects (lzcnt(x) >> log2(bitsizeof_x)) == ( x == 0)
Added set_srcN(value, idx) which can be used to set the nth source of an instruction, which makes more sense than having three different functions that only differ by the field they touch
Added Value::VisitValueOperands for iterating all Value operands an instruction has.
Add BackpropTruncations code to simplification_pass
Changed the (void**) dereferences of raw_context that are done to grab thread_state to instead reference PPCContext and the thread_state field. Moved the thread_state field to the tail of PPCContext.
Moved membase to the tail of PPCContext, since now it is reloaded very infrequently.
Rearranged PPCContext so that the condition registers come first (most accesses to them cant get SSA'd), moved lr and ctr to after gp regs since they are not accessed as much as the main gpregs. This way the most frequently
accessed registers will be accessible via a rel8 displacement instead of rel32 (ideally, we would have only certain CRs at the start, but xenia does pointer arithmetic on CR0's offset to get CRn)
Use alignas(64) to ensure PPCContext's padding
Map PPCContext specially so that the low 32 bits of the context register is 0xE0000000, for the 4k page offset check. Also allocate the page before, so that backends can store their own information that is not relevant to the PPCContext on that page and
reference that data in the generated asm via 8-bit signed displ or 32-bit signed displ. Currently this page is not being utilized, but I plan on stashing some data critical to the x86 backend there
Changed many wrong avx instructions, they worked but they were not intended for the data they operated on, meaning they transferred domains and caused 1-2 cycle stall each time
Added SimdDomain checking/deduction to X64Emitter.
Used SimdDomain code to fix a lot of float/int domain stalls

Use the low 32 bits of the context register instead of constant 0xE0000000 in ComputeAddress
Special path for SELECT_V128 with result of comparison that will use a blend instruction instead of and/or
Many HIR optimizations added in simp pass
A bunch of other stuff running out of time to write this msg
2022-07-17 09:52:40 -07:00
Triang3l e8652e544a [GPU] Translucent trace viewer controls 2022-07-17 17:29:41 +03:00
Triang3l 25663827ba [GPU] Trace viewer Android content URI loading 2022-07-17 16:37:49 +03:00
Triang3l 624f2b2d9e [Base] Android content URI file memory mapping 2022-07-17 16:34:17 +03:00
Triang3l 93a7918025 [Base] Android content URI file descriptor opening 2022-07-17 16:25:58 +03:00
Triang3l 34a952d789 [Base] Wrap strdup and strcasecmp in xe:: functions 2022-07-17 16:14:29 +03:00
chss95cs@gmail.com 6a612b4d34 remove useless tag field from hir::Value
pack local_slot and constant in hir::Value
Instead of loading membase at the start of every function, just load it in HostToGuestThunk
vzeroupper in GuestToHostThunk before calling host function, and in HostToGuestThunk after calling function to prevent AVX dirty state slowdowns. In the future, check if CPU implements AVX as 128x2 and skip if so (https://john-h-k.github.io/VexTransitionPenalties.html)
Remove useless save/restore of ctx pointer, nothing modifies it and it prevents cpus from doing cross-function memory renaming (https://www.agner.org/forum/viewtopic.php?t=41). Could not remove the space on stack because of alignment issues, instead turned it into GUEST_SCRATCH64 which is a temporary that sequences may use
Reorder OpcodeInfo so that name is at offset 0, remove name and add GetOpcodeName function (name is only used for debug code, we are seperating frequently accessed data and rarely accessed data)
Add VECTOR_DENORMFLUSH opcode for handling output to DOT_PRODUCT and other opcodes that implicitly force denormal inputs/outputs to zero, will eventually use for implementing NJM
Rewrite sequences for LOAD_VECTOR_SHL/SHR. The mask with 0xf in it was pointless as all InstrEmit_ functions that create the load shift instructions do that in HIR. The tables are only used for nonzero constant inputs now, which are probably pretty rare. Instead of doing a shift and lookup, a base value is used for both in the constant table and adding/subtracting of the input is done
Reuse result of LoadVectorShl/Shr in InstrEmit_stvlx_, InstrEmit_stvrx_. We were previously calculating it twice which was contributing to the final sequences' fatness. Use OPCODE_SELECT instead of the sequence of or, andnot, and that it was using for merging
Add the proper unconditional denormal input flushing behavior to vfmadd, add it also to vfmsub (making the assumption it has the same behavior)
Remove constant propagation for DOT_PRODUCT_3/4
DOT_PRODUCT_3/4 now returns a vector with all four elements set to the result. (what we were doing before, truncating to float32 and then splatting didnt make any sense)
Add much more correct versions of DOT_PRODUCT_3/4, matching the Xb360's  to 1 bit. Still needs work to be a perfect emulation.
Add constant folding for OPCODE_SELECT, OPCODE_INSERT, OPCODE_PERMUTE, OPCODE_SWIZZLE
Remove constant folding for DOT_PRODUCT
Removed the multibyte nop code I committed earlier, it doesnt help us much because nops are only used for debug stuff and its ugly and wouldnt survive in a pr to main
Check for AVX512BMI, use vpermb to shuffle if supported
2022-07-16 10:25:04 -07:00
Triang3l 500bbe9e0d [Base] Use to_path for Android path argument loading 2022-07-16 13:42:04 +03:00
Triang3l 373b143049 [Base] Cvars from Android Bundle/Intent 2022-07-16 13:13:08 +03:00
chss95cs@gmail.com 71c5f8f0fa Optimized GetScalarNZM, add limit to how far it can recurse. Add rlwinm elimination rule 2022-07-14 14:32:14 -07:00
Triang3l 415750252b [Base] PosixMappedMemory: Close, Flush 2022-07-14 22:51:07 +03:00
Triang3l 65137e58bd [Base] PosixMappedMemory: fd instead of stdio
Android ContentResolver, which is needed for content:// URIs, provides file descriptors rather than stdio files
2022-07-14 22:11:46 +03:00
Triang3l 9fd63519bf [Base] Make MappedMemory non-copyable 2022-07-14 22:04:06 +03:00
Triang3l 2a69d1db4d [Vulkan] Fix a typo in a comment about BC textures [ci skip] 2022-07-14 21:16:23 +03:00
Triang3l 7b8281aee0 [UI] Android ImGui touch and mouse input 2022-07-14 21:13:40 +03:00
Triang3l 037310f8dc [Android] Unified xenia-app with windowed apps and build prerequisites 2022-07-11 21:45:57 +03:00
Gliniak 1d00372e6b Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-10 10:50:39 +02:00
Triang3l b41bb35a20 [SPIR-V] Make interpolators an array to fix Adreno linkage 2022-07-09 17:52:26 +03:00
Triang3l b3edc56576 [Vulkan] Merge texture and sampler descriptors into a single descriptor set
Put all descriptors used by translated shaders in up to 4 descriptor sets, which is the minimum required, and the most common on Android, `maxBoundDescriptorSets` device limit value
2022-07-09 17:10:28 +03:00
Gliniak d33be73f3d Fixed crash caused by hash calculation in specific cases 2022-07-08 08:49:43 +02:00
Triang3l e4de8663c4 [Vulkan] All guest draw uniform buffer bindings in a single descriptor set
Reduce the number of bound descriptor sets from 10 to 6, which is still above the minimum limit of 4, but closer
2022-07-07 21:05:56 +03:00
Triang3l 88c055eb30 [CPU] Null backend enough for GPU trace viewing 2022-07-06 23:28:06 +03:00
Triang3l 3ee68d79ea Revert "[GPU] Make Processor optional for GraphicsSystem setup"
The Processor is still required in many places, including the GPU command processor worker thread

This reverts commit fd03d886e9.
2022-07-06 22:43:40 +03:00
Triang3l 6852e54937 [CPU] Remove intrinsics from dot product constant propagation 2022-07-06 21:32:56 +03:00
Triang3l 326e718035 [CPU] MMIO: Arm64, load register writes + exception cleanup 2022-07-06 21:05:05 +03:00
Triang3l fd03d886e9 [GPU] Make Processor optional for GraphicsSystem setup 2022-07-05 21:21:22 +03:00
Triang3l bdfd410b13 [CPU] Cleanup x64 backend usage conditionals 2022-07-05 21:07:10 +03:00
Triang3l d263d508cd [GPU] Make operator< const 2022-07-05 20:47:53 +03:00
Triang3l 536f14d94c [GPU] Fix a typo in a Neon intrinsic name 2022-07-05 20:47:34 +03:00
Triang3l d51fafd07c [Base] Linux Arm64 exception handler 2022-07-05 20:46:49 +03:00
Triang3l 40aa73f7d7 [Linux] Swap read/write in x64 page fault handler + exception code cleanup 2022-07-04 23:51:26 +03:00
Triang3l a9cbd9cc5f [Linux] Update RIP after handling an exception 2022-07-04 23:24:26 +03:00
uytvbn 54aac81268 [Linux] Implement exception handler 2022-07-04 23:04:27 +03:00
Triang3l 35d4ea59c6 [Base] Remove exception_handler_linux.cc 2022-07-04 23:02:11 +03:00
Triang3l feaad639fb [Vulkan] Destroy all RTs before VulkanRenderTargetCache is destroyed 2022-07-04 11:27:51 +03:00
Gliniak 6e753c6399 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-04 08:11:04 +02:00
Triang3l 2621dabf0f [Vulkan] Native 24-bit unorm depth where available 2022-07-03 21:21:17 +03:00
Triang3l 83e9984539 [Vulkan] Remove required feature checks
Fallbacks for those will be added more or less soon, the stable version won't hard-require anything beyond 1.0 and the portability subset
2022-07-03 20:54:34 +03:00
Triang3l bbae909fd7 [GPU] Reasons to keep non-Vulkan backends [ci skip] 2022-07-03 20:39:44 +03:00
Triang3l ed61e15fc3 [App] Make D3D12 the default GPU backend on Windows again 2022-07-03 19:49:11 +03:00
Triang3l ee84f4e267 [Vulkan] Update title bar warning 2022-07-03 19:45:48 +03:00
Triang3l f7ef051025 [Vulkan] Disable validation by default 2022-07-03 19:42:22 +03:00
Triang3l 001f64852c [Vulkan] VMA for textures 2022-07-03 19:40:48 +03:00
Gliniak a8df744ea6 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-07-03 13:07:15 +02:00
Triang3l 636585e0aa [Vulkan] Trace viewer 2022-07-01 19:53:41 +03:00
Triang3l ad1ef84145 Merge branch 'master' into vulkan 2022-07-01 19:53:08 +03:00
Triang3l e37e3ef382 [GPU] Display swap output in the trace viewer
Resolve output is unreliable because resolving may be done to a subregion of a texture and even to 3D textures, and to any color format
2022-07-01 19:50:19 +03:00
Triang3l c8a4a9504f [Vulkan] Remove an unneeded scale from RefreshGuestOutput aspect ratio 2022-07-01 12:52:12 +03:00
Triang3l d174762a40 Merge branch 'master' into vulkan 2022-07-01 12:51:34 +03:00
Triang3l 28670d8ec2 [UI] Presenter: Rename display size to aspect ratio 2022-07-01 12:50:45 +03:00
Triang3l f8b351138e [Vulkan] Alpha test 2022-06-30 22:20:51 +03:00
Triang3l 6772c88141 Merge branch 'master' into vulkan 2022-06-30 22:15:29 +03:00
Triang3l 7e691d5ef1 [DXBC] Handle NaN in not equal alpha test as passed 2022-06-30 22:15:01 +03:00
Triang3l c0c3666e12 [Vulkan] Align texture extents in loading to vector size accessed by the shader
Fixes loading of the 1x1 linear 8_8_8_8 texture containing just a single #FFFFFFFF texel in 4D5307E6, which is used for screen fade and the lobby map loading bar background
2022-06-29 23:41:32 +03:00
Triang3l 9392fff369 Merge branch 'master' into vulkan 2022-06-29 23:39:54 +03:00
Triang3l a11b070fee [GPU] Align texture extents in loading to host buffer texel size accessed by the shader 2022-06-29 23:38:06 +03:00
Triang3l 7c2df55209 [Vulkan] Cache clear: shared memory, scratch buffer 2022-06-29 13:24:45 +03:00
Triang3l d5815d9e6a [Vulkan] Float24 depth range remapping fixes 2022-06-29 13:14:00 +03:00
Gliniak efe3cd96d6 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-29 09:21:09 +02:00
Triang3l 05ef7a273a [Vulkan] Samplers (only 1.0 core features for now) 2022-06-28 22:42:18 +03:00
Triang3l 5d9061cf99 Merge branch 'master' into vulkan 2022-06-28 22:05:45 +03:00
Triang3l 243683d2e9 [GPU] Cleanup Texture::MarkAsUsed conditionals 2022-06-28 22:04:26 +03:00
Triang3l 382710bab7 [GPU] Normalize sampler clamp modes 2022-06-28 21:58:58 +03:00
Triang3l cedc94679b [GPU] Don't drop the rest of the command list if IssueDraw fails 2022-06-28 21:40:06 +03:00
chss95cs@gmail.com 3c06921cd4 Added optimizations for combining conditions together when their results are OR'ed
Added recognition of impossible comparisons via NZM and optimize them away
Recognize (x + -y) and transform to (x - y) for constants
Recognize (~x ) + 1 and transform to -x
Check and transform comparisons if theyre semantically equal to others
Detect comparisons of single-bit values with their only possible non-zero value and transform to true/false tests
Transform ==0 to IS_FALSE, !=0 to IS_TRUE
Truncate to int8 if operand for IS_TRUE/IS_FALSE has a nzm of 1
Reduced code generated for SubDidCarry slightly
Add special case for InstrEmit_srawix if mask == 1
Cut down the code generated for trap instructions, instead of naive or'ing or compare results do a switch and select the best condition
Rerun simplification pass until no changes, as some optimizations will enable others to be done
Enable rel32 call optimization by default
2022-06-26 12:49:04 -07:00
Gliniak e6898fda66 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-26 20:11:33 +02:00
chrisps 08232de8cc
patch a mistake in NZM calculation for OPCODE_NOT 2022-06-26 09:30:56 -07:00
Triang3l 9672230d9f Merge branch 'master' into vulkan 2022-06-26 18:59:49 +03:00
Triang3l ec008463b6 [GPU] CrYCb/YCrCb border colors 2022-06-26 18:56:50 +03:00
Triang3l 2606fa5709 [GPU] Apply BaseMap MipFilter via samplers as it may be overridden
Make it have no effect on the texture resource as a resource may be used with samplers with different overrides. Also make sure magnification vs. minification is not undefined with it on Direct3D 12.
2022-06-26 18:41:38 +03:00
Triang3l e191430091 Merge branch 'master' into vulkan 2022-06-26 16:58:27 +03:00
Triang3l 086a070fa9 [GPU] Explicitly cast bit field values in std::min/max
According to the integral promotion rules https://eel.is/c++draft/conv.prom#5.sentence-1 bit fields can be promoted to `int` if it's wide enough to store their value, and then otherwise, to `unsigned int`. Hopefully fixes Clang building (the `width_div_8` case).
2022-06-26 16:54:11 +03:00
Triang3l e0b890fe5c [DXBC] Remove alphatest/A2C with [earlydepthstencil] 2022-06-26 15:31:08 +03:00
Triang3l 6688b13773 [Vulkan] PsParamGen 2022-06-26 15:01:27 +03:00
Triang3l a99a1be880 Merge branch 'master' into vulkan 2022-06-26 15:00:21 +03:00
Triang3l b787f2dec1 [GPU] GPR count limit is 128, not 64 2022-06-26 14:45:49 +03:00
Triang3l a5c8df7a37 [Vulkan] Remove UB-based independent blend logic
On Vulkan, unlike Direct3D, not writing to a color target in the fragment shader produces an undefined result.
2022-06-25 20:57:44 +03:00
Triang3l d8b2944caa [Vulkan] Handle unsupported fillModeNonSolid + fix portability subset feature checks 2022-06-25 20:46:52 +03:00
Triang3l d30d59883a [Vulkan] Color exponent bias and gamma conversion 2022-06-25 20:35:13 +03:00
Triang3l b1be33004a Merge branch 'master' into vulkan 2022-06-25 20:31:26 +03:00
Triang3l 4812b4ba8b [D3D12] Fix outdated color system constants comment [ci skip] 2022-06-25 20:31:05 +03:00
chss95cs@gmail.com 327cc9eff5 drastically reduce size of final generated code for rlwinm by adding special paths for rotations of 0, masks that discard the rotated bits and using And w/ UINT_MAX instead of truncate/zero extend
Add special case to TYPE_INT64's EmitAnd for UINT_MAX mask. Do mov32 to 32 if detected to take advantage of implicit zero xt/reg renaming

Add helper function for skipping assignment defs in instr.
Add helper function for checking if an opcode is binary value type
Add several new optimizations to simplificationpass, plus weak NZM calculation code (better full evaluation of Z/NZ will be done later) .
 List of optimizations:
  If a value is anded with a bitmask that it was already masked against, reuse the old value (this cuts out most FPSCR update garbage, although it does cause a local variable to be allocated for the masked FPSCR and it still repeatedly stores the masked value to the context)
  If masking a value that was or'ed against another check whether our mask only considers bits from one value or another. if so, change the operand to the OR input that actually matters
  If the only usage of a rotate left's output is an AND against a mask that discards the bits that were rotated in change the opcode to SHIFT_LEFT
  If masking against all ones, become an assign.
  If XOR or OR against 0, become an assign (additional FPSCR codegen cleanup)
  If XOR against all ones, become a NOT
Adding a direct CPUID check to x64_emitter for lzcnt, the version of xbyak we are using is skipping checking for lzcnt on all non-intel cpus, meaning we are generating the much slower bitscan path for AMD cpus.
2022-06-25 09:58:13 -07:00
Triang3l 5dca11a892 [SPIR-V] Fix fetch constant LOD bias signedness 2022-06-25 16:33:35 +03:00
Triang3l d8b0227cbd [SPIR-V] Fix cubemap X axis 2022-06-25 16:25:29 +03:00
Triang3l fdcbf67623 [Vulkan] Enable VK_KHR_sampler_ycbcr_conversion 2022-06-25 15:46:02 +03:00
Triang3l 758db4ccb3 [Vulkan] Fix textures not loaded if using a shader for the first time 2022-06-25 15:15:06 +03:00
Triang3l 4db445c6f9 Merge branch 'master' into vulkan 2022-06-25 15:13:41 +03:00
Triang3l aa45d7b47d [D3D12] More descriptive pipeline creation call comment [ci skip] 2022-06-25 15:13:11 +03:00
Triang3l c37c05d189 [Vulkan] Remove an outdated fullscreen shader comment [ci skip] 2022-06-25 14:35:15 +03:00
Triang3l 4b4205ba00 [Vulkan] Frontbuffer presentation 2022-06-25 14:33:43 +03:00
Triang3l 3fc7d8753c Merge branch 'master' into vulkan 2022-06-24 23:38:04 +03:00
Triang3l f4a634c617 [XeSL] xesl_write*Store > xesl_*Store 2022-06-24 23:37:29 +03:00
Triang3l 7a4732e14f [GPU] XeSL swap shaders 2022-06-24 23:24:30 +03:00
Gliniak 2b3686f0e9 [XAM] Set profile setting 'from' entry accordingly to setting existence 2022-06-24 10:10:52 +02:00
Triang3l b7737d70ca [D3D12] Update RequestSwapTexture resource state comment [ci skip] 2022-06-23 22:59:53 +03:00
Gliniak ce3b159683 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-22 21:05:45 +02:00
Triang3l 227d495738 Merge branch 'master' into vulkan 2022-06-22 21:19:29 +03:00
Triang3l e9f129f67f [GPU] Safer and more correct depth bias conversion
Float24-as-float32 depth bias is now in the increments of 8, because conversion of the depth to float24 directly in the pixel shaders may destroy the bias qualitatively otherwise if it's too small.
2022-06-22 21:14:40 +03:00
Triang3l a7885ae1a4 [GPU] Fix CPU-side float24 conversion broken recently 2022-06-22 20:47:44 +03:00
Triang3l 4514050f55 [Vulkan] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 13:25:06 +03:00
Gliniak e7a122d943 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-22 12:18:13 +02:00
Triang3l 0d8bd0e0c6 Merge branch 'master' into vulkan 2022-06-22 13:15:50 +03:00
Triang3l cbf0476d42 [D3D12] Don't round float24 depth when it's known to be exact 2022-06-22 13:14:38 +03:00
Gliniak 83269315d8 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-22 12:06:42 +02:00
Triang3l 7869b080d3 [D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Gliniak 87fd772393 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-21 07:54:44 +02:00
chss95cs@gmail.com 549ee28a93 ome guest function calls can now be resolved and embedded directly in
the emitted asm as rel32 calls. Disabled by default, enabled via
resolve_rel32_guest_calls
detect whether cpu has fast jrcxz, fast loop/loope/loopne
much more thorough LoadConstantXMM
New cvar elide_e0_check that allows the backend to assume accesses via
the SP or TLS register will not cross into 0xe0 range
Add x64 codegen for Vector shift uint8
If has fast jrcxz use for some traptrue/breaktrue instructions
Use phat nops
Add cvar use_fast_dot_product, which uses a four instruction sequence
for both dot product instructions which ought to be equivalent. disabled
by default.
2022-06-20 15:08:18 -07:00
Triang3l c0703e64db Merge branch 'master' into vulkan 2022-06-20 22:40:19 +03:00
Triang3l e2f632f8fa [D3D12] Use udiv by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
2022-06-20 22:39:30 +03:00
Triang3l 0dc480721f [Vulkan] Render target resolving 2022-06-20 22:29:07 +03:00
Triang3l c6ec6d8239 [Vulkan] Use UDiv/UMod by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
2022-06-20 22:24:07 +03:00
Gliniak a4ff64c465 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-20 21:07:32 +02:00
Triang3l 61c4c49d76 Merge branch 'master' into vulkan 2022-06-20 12:34:41 +03:00
Triang3l 207e11c8d2 [GPU] Separate range arguments for fixed16 RG and RGBA in GetResolveInfo
On Vulkan, when snorm16 in unsupported, these formats may be emulated as float16, which natively can represent a wide range of numbers including -32 to 32 with blending. However, R16G16_SNORM and R16G16B16A16_SNORM are two separate formats, which may have different support on the device.
2022-06-20 12:29:45 +03:00
Triang3l 3b4845511d [Vulkan] Don't require an explicit uint64_t cast for SetDeviceObjectName 2022-06-20 12:25:52 +03:00
Triang3l 67ff108f53 [Vulkan] Explain why CreateShaderModule takes uint32_t* [ci skip] 2022-06-20 12:22:41 +03:00
Triang3l b61953374e [GPU] Make resolve EDRAM binding DS 0 and rename it
Ordering the descriptor sets by the change frequency on Vulkan, in increasing order (the opposite of D3D12 root signatures). The EDRAM binding never changes there (always one storage buffer), while the destination buffer binding may become changeable in the future (to split dispatches if exceeding `maxStorageBufferRange`, for example).
2022-06-20 12:15:52 +03:00
Triang3l 1200b205cf Merge branch 'master' into vulkan 2022-06-19 17:52:28 +03:00
Triang3l 9b83d3d0f4 [GPU] XeSL resolve shaders + host depth store width fix 2022-06-19 17:50:21 +03:00
Gliniak 1e369afa3d [Memory] Allocate system heap memory from bottom of heap last quarter
Aka. From 0x30000000
2022-06-17 22:23:39 +02:00
Gliniak 0b183a3582 Merge branch 'chris_cpu_changes' of https://github.com/Gliniak/xenia.git into canary_experimental 2022-06-17 14:04:58 +02:00
chrisps e4fd015886 Juicy optimization goodness 2022-06-17 14:03:24 +02:00
chss95cs@gmail.com 8a8ff6ae46 Reuse flag results in OPCODE_BRANCH_TRUE codegen if the preceding instruction was a comparison that already set the cpu flags 2022-06-17 11:13:49 +02:00
chss95cs@gmail.com 3675b3860a Add constant folding for OPCODE_ROTATE_LEFT 2022-06-17 11:12:49 +02:00
chrisps 3ad80810b5 Optimized CONVERT_I64_TO_F64 with neat overflow trick
Reduced instruction count from 11 to 8, eliminated a movq stall.
2022-06-17 11:10:48 +02:00
chrisps 9dfbef8acf Smaller ComputeMemoryAddress/Offset sequence
Replace a movzx after setae in both ComputeMemoryAddressOffset and ComputeMemoryAddress with a xor_ of eax prior to the cmp. This reduces the length in bytes of both sequences by 1, and should be a moderate ICache usage reduction thanks to the frequency of these sequences.
2022-06-17 11:10:27 +02:00
Gliniak c0483f8bee Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-17 10:58:15 +02:00
Triang3l 166be463be [XeSL] Metal Shading Language definitions 2022-06-16 21:39:16 +03:00
Gliniak e8aaddf4d5 Merge remote-tracking branch 'GliniakRepo/patchingSystem' into canary_experimental 2022-06-14 17:50:25 +02:00
Triang3l 127bf34264 [Vulkan] Trace dump tool 2022-06-13 13:03:02 +03:00
Gliniak 91f43a374d Initial support for xex patching 2022-06-12 20:10:07 +02:00
Gliniak 945976a31d Added Premake Files For PatchingSystem 2022-06-12 19:58:12 +02:00
Triang3l ac268afbe9 [Vulkan] Fix 1<< uint32_t constants 2022-06-12 19:45:12 +03:00
Triang3l 140ed51e9a [GPU] Fix missing xenia-ui dependency in gpu > gpu-shader-compiler (needed for gmake2) 2022-06-12 19:44:24 +03:00
Triang3l 17c835b245 Merge branch 'master' into vulkan 2022-06-12 18:51:08 +03:00
Triang3l 820b7ba217 [GPU] Fix GetActiveTextureHostSwizzle return type 2022-06-12 18:50:38 +03:00
Gliniak 90d67ac11c [Kernel] Return X_STATUS_END_OF_FILE for async file read when offset > file_size 2022-06-09 21:36:09 +02:00
Triang3l 1a22216e44 [SPIR-V] Texture fetch instructions 2022-06-09 21:42:16 +03:00
Triang3l f875a8d887 Merge branch 'master' into vulkan 2022-06-09 21:35:12 +03:00
Triang3l 78d1eb8bf8 [GPU] TextureCache::GetActiveTextureHostSwizzle 2022-06-09 21:34:21 +03:00
Gliniak d0175ddf2f [XAM] Cut handle mask from socket handles, added support for: NetDll_getsockopt
Only positive values should be interpreted as valid sockets!
2022-06-08 19:59:15 +02:00
Gliniak 25f3e16baa [Patcher] Fixed issue with incorrect patches endianness 2022-06-08 19:42:18 +02:00
Gliniak 0de0f40fb5 [XAM] Added stubs for:
- NetDll_XNetCreateKey
 - NetDll_XNetRegisterKey

This will allow certain games to run local multiplayer
For example PDZ Deathmatch mode
2022-06-07 20:46:47 +02:00
Triang3l 56f72da137 [GPU] More exact PWL texture/RT gamma conversion 2022-06-07 21:26:34 +03:00
Gliniak 916eb1b9bd [XAM] Scan every controller slot if provided flags contains USER_ANY flag 2022-06-07 15:52:41 +02:00
Margen67 5701823ccf Log title_name 2022-06-07 09:43:04 +02:00
jgoyvaerts 5296d2e91e Fix xenia.log file not always being created in the executable folder. 2022-06-07 09:41:52 +02:00
Gliniak c7da7e1999 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-02 22:19:43 +02:00
Triang3l a8cfe9bebb [Vulkan] Unsubsample odd-sized 4:2:2 textures 2022-06-02 23:10:50 +03:00
Triang3l 1ce45ee150 Merge branch 'master' into vulkan 2022-06-02 22:50:14 +03:00
Triang3l 55a91afcc7 [D3D12] Don't decompress unaligned BC textures if supported 2022-06-02 22:48:03 +03:00
Triang3l 84fcd5defa [GPU] Fix resolve destination offset and extent calculation 2022-06-02 21:47:30 +03:00
Triang3l a9a072bf00 [GPU] Explain why a 32x32x4bpp linear texture takes 2 pages, not 1 [ci skip] 2022-06-01 13:00:23 +03:00
Triang3l 8bd244f277 [GPU] Better explanation for exact texture memory extent calculation [ci skip] 2022-06-01 12:55:16 +03:00
Gliniak 3169aa2ff3 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-06-01 08:45:21 +02:00
Triang3l d1ad10b98c [GPU] Primitive reset comment typo correction [ci skip] 2022-05-31 23:23:53 +03:00
Triang3l efd7ef212a [D3D12] 128 megatexel limit explanation based on the spec [ci skip] 2022-05-31 23:23:10 +03:00
Triang3l 25594c918c [GPU] Fix tiled texture memory extent calculation 2022-05-31 23:17:33 +03:00
Rick Gibbed a3e5ea8575
[Base] Fix missing include in utf8.cc. 2022-05-27 17:56:14 -05:00
Gliniak 5a71b55233 [Kernel] Added missing module hash calculation 2022-05-25 09:03:03 +02:00
Gliniak 542e075699 Fixed bug between reading header content and applying TUs 2022-05-25 08:23:19 +02:00
Gliniak d7d26dc1c4 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-05-25 07:54:16 +02:00
Gliniak 3d96dfa359 Always allocate system heap from top of heap 2022-05-25 07:53:50 +02:00
Triang3l 6c9a06b2da [Vulkan] Texture loading 2022-05-24 22:42:22 +03:00
Triang3l 9c445d397b [Vulkan] Fix single-type descriptor pool reuse 2022-05-24 22:37:49 +03:00
Triang3l aac28f19d1 Merge branch 'master' into vulkan 2022-05-24 22:34:40 +03:00
Triang3l a4840e1992 [GPU] FIXME comment for 1bpb/2bpb texture tiled extent 2022-05-24 22:33:27 +03:00
Triang3l 8701c9f24e [D3D12] Texture load code cleanup and resolution scaling fixes
The resolution scale is now taken into account when copying from the mip tail.
2022-05-24 22:28:42 +03:00
Triang3l 75c185e759 [GPU] Move texture load shader info to common 2022-05-24 22:24:33 +03:00
Triang3l f994d3ebb3 [Vulkan] Single block-compressed flag for host texture formats, not block sizes 2022-05-23 13:27:43 +03:00
Triang3l f7b0edee6b [Vulkan] GBGR/BGRG decompression 2022-05-23 13:18:47 +03:00
Triang3l 4c2f8764d6 Merge branch 'master' into vulkan 2022-05-23 12:36:35 +03:00
Triang3l c1f15c86a3 [GPU] Decompress GBGR/BGRG into RGBB, not RGB1
While the alpha of the texture data is not used at all (replaced with blue using the view swizzle), still make the shader code state the intention more explicitly if the format is decompressed for use as signed. Unsigned 1.0 is 0xFF, while signed 1.0 is 0x7F.
2022-05-23 12:31:45 +03:00
Triang3l cf3069eb13 [GPU] Signedness in Cr_Y1_Cb_Y0_REP/Y1_Cr_Y0_Cb_REP comment [ci skip] 2022-05-22 22:11:59 +03:00
Triang3l ef808e9def [GPU] _REP explanation in Cr_Y1_Cb_Y0_REP/Y1_Cr_Y0_Cb_REP comment [ci skip] 2022-05-22 21:46:11 +03:00
Triang3l 6735dbd941 [GPU] Calculate, not store, texture load host X blocks per thread 2022-05-22 21:21:54 +03:00
Triang3l 888d5044e0 [GPU] 2x1-subsampled texture RGBA8 conversion shader 2022-05-22 21:07:38 +03:00
Triang3l d3561d2f47 [D3D12] Pre-swizzle 2x1-subsampled formats 2022-05-22 20:31:48 +03:00
Triang3l 5de825e3a0 [GPU] Prevent multiple evaluation of XE_TEXTURE_LOAD_TRANSFORM arguments 2022-05-22 19:48:23 +03:00
Triang3l 2f0a884438 [GPU] Add k prefix to texture load group size constants 2022-05-22 19:35:25 +03:00
Triang3l 8f06ba6f7d [D3D12] Texture host BPB in LoadModeInfo 2022-05-22 19:28:05 +03:00
Triang3l 003c62ba73 [GPU] Correct rounding of texture load row size
The original multiplication was likely added early during the development of generic resolution scaling. Before generic resolution scaling, invocations were done for unscaled guest blocks, now they're done for scaled blocks, so with 3x1 scaling, an invocation for 8 blocks writes 8 host blocks, not 24.
2022-05-22 18:33:59 +03:00
Triang3l 6aa30ed074 [GPU] 128-thread groups in all texture load shaders
Vulkan's minimum requirement (maxComputeWorkGroupInvocations) is 128.
2022-05-22 18:03:09 +03:00
Triang3l 91c4e02e96 [Vulkan] Implement ClearCaches and don't do it for pipelines 2022-05-22 15:05:15 +03:00
Triang3l 35cfb07967 Merge branch 'master' into vulkan 2022-05-22 14:56:44 +03:00
Triang3l 88784101c8 [D3D12] Remove PipelineCache::ClearCache leftovers 2022-05-22 14:56:22 +03:00
Triang3l 68e7c56918 Merge branch 'master' into vulkan 2022-05-22 14:47:20 +03:00
Triang3l d31ddd9b23 [GPU] Remove PipelineCache::ClearCache 2022-05-22 14:46:03 +03:00
Gliniak dde8adc140 Allow XamUserReadProfileSettings to use xuid to define profile 2022-05-22 13:11:29 +02:00
Gliniak 84e5b159c3 Do not store obsolete info about deleted threads 2022-05-22 13:11:21 +02:00
Gliniak b759cb23a5 Better handling of title workspace 2022-05-22 13:11:08 +02:00
Gliniak 4bfd3a6506 Reset state of event before executing overlap code 2022-05-22 13:09:37 +02:00
Gliniak 5784e7bc8d Send signin changed notification for primary user 2022-05-22 13:09:25 +02:00
Gliniak 620aa3562e Set system page blocks to gpu-written every frame 2022-05-22 13:09:12 +02:00
Gliniak ba60b94c7d Round size to 64k for allocations without base address 2022-05-22 13:09:01 +02:00
Gliniak af806ee98f Allocate guest objects in last quarter of memory heap 2022-05-22 13:08:47 +02:00
Gliniak 7be4b7a138 Increase profiler max threads to 256 2022-05-22 13:06:50 +02:00
Gliniak a190bf9fd8 Changed max component length for host and svod types 2022-05-22 13:06:42 +02:00
Triang3l 08769de68b [Vulkan] Texture object and view creation 2022-05-19 21:56:24 +03:00
Triang3l b0e1916f75 Merge branch 'master' into vulkan 2022-05-19 21:46:21 +03:00
Triang3l 9aaf19a455 [Vulkan] Remove unused variable in VulkanPresenter::GuestOutputImage::Initialize 2022-05-19 21:45:48 +03:00
Triang3l c85c2f5b79 Merge branch 'master' into vulkan 2022-05-19 21:43:19 +03:00
Triang3l 1dcc919a33 [GPU] Move k_Y1_Cr_Y0_Cb_REP usage example to xenos.h 2022-05-19 21:41:52 +03:00
Triang3l 7d63d6e1d3 [D3D12] Fix 2:1-subsampled format swizzle 2022-05-19 21:40:03 +03:00
Triang3l 825a5b176c [D3D12] Fix frontbuffer resource state 2022-05-19 21:39:11 +03:00
Gliniak 5ce75a1479 Merge remote-tracking branch 'GliniakRepo/xam_swap_disc' into canary_experimental 2022-05-19 12:07:05 +02:00
Gliniak f21dbc66ba Implemented XamSwapDisc 2022-05-19 12:04:32 +02:00
Gliniak db50db3215 Merge remote-tracking branch 'GliniakRepo/TU_APPLY' into canary_experimental 2022-05-19 11:00:34 +02:00
Gliniak 7c2cd16548 Merge remote-tracking branch 'GliniakRepo/local_multiplayer' into canary_experimental 2022-05-19 10:56:21 +02:00
Gliniak 6c6c5ac14b Merge remote-tracking branch 'GliniakRepo/experimentals' into canary_experimental 2022-05-19 10:51:44 +02:00
Philpax e901567193 Fix crash from null sample channel
Certain games, such as Forza Motorsport 3, submit XMA data with the
stereo flag set with a null second channel. This falls back to mono
conversion when the second channel is null, preventing a crash.
2022-05-19 10:22:41 +02:00
Margen67 64b336805e Add vsync_interval option 2022-05-19 10:22:32 +02:00
Gliniak 0881725533 Merge remote-tracking branch 'GliniakRepo/const_prop_opcode_and_not' into canary_pr 2022-05-19 10:18:58 +02:00
Gliniak 75f0dfd6f3 Merge remote-tracking branch 'GliniakRepo/deleteFunctionsFromUnloadedModule' into canary_pr 2022-05-19 10:18:18 +02:00
Gliniak 320cbc43c8 Merge remote-tracking branch 'GliniakRepo/physicalProtectPageCombinations' into canary_pr 2022-05-19 10:17:58 +02:00
Gliniak ef281c69c3 Merge remote-tracking branch 'GliniakRepo/xamNetSockNameAndErrorHandling' into canary_pr 2022-05-19 10:17:29 +02:00
Gliniak de03165995 Merge remote-tracking branch 'GliniakRepo/audioSkipHeaderInputOffset' into canary_pr 2022-05-19 10:16:41 +02:00
Gliniak 5ef92faf6d Merge remote-tracking branch 'GliniakRepo/createEnumeratorHandle' into canary_pr 2022-05-19 10:16:10 +02:00
Gliniak 006f3adad3 Merge remote-tracking branch 'GliniakRepo/disablePositiveVibes' into canary_pr 2022-05-19 10:03:50 +02:00
Gliniak b237b71031 Merge remote-tracking branch 'GliniakRepo/memory_stats' into canary_pr 2022-05-19 10:03:29 +02:00
Gliniak 7ac2279d34 Merge remote-tracking branch 'GliniakRepo/customConHeaderImplementation' into canary_pr 2022-05-19 10:03:05 +02:00
Gliniak 5247220e73 Merge remote-tracking branch 'GliniakRepo/patchingSystem' into canary_pr 2022-05-19 10:01:33 +02:00
Margen67 99e3a1a4b1 Disable Vulkan 2022-05-19 09:39:58 +02:00
illusion0001 f9fd3e5fec AVPack cvar 2022-05-19 09:39:56 +02:00
illusion 357d9adfca automatic aspect ratio change
aspect ratio will now change if internal resolution is set to anything 4:3
(i.e 640x480, 1024x768, 1600x1200.. etc.)
2022-05-19 09:39:56 +02:00
Margen67 bdd431cd4a Rename exe to xenia_canary 2022-05-19 09:39:55 +02:00
illusion98 7242efdeef Change default config file name 2022-05-19 09:39:55 +02:00
illusion98 471041a9b5 Change window title
xenia -> xenia-canary
2022-05-19 09:39:55 +02:00
illusion98 6036c977e8 Change ID and new description 2022-05-19 09:39:55 +02:00
illusion98 c0333ea7c6 Add Time Elasped and Description Text
Display Time Elapsed when idle or playing a game
Display description when hovering over the icon
2022-05-19 09:39:55 +02:00
Triang3l 46202dd27a [Vulkan] Basic texture descriptor set allocation/binding 2022-05-17 22:42:28 +03:00
Triang3l 3381d679b4 Merge branch 'master' into vulkan 2022-05-17 22:31:34 +03:00
Triang3l 7675b6b140 [DXBC] Cleanup texture/sampler name setting 2022-05-17 22:30:55 +03:00
Triang3l 533de3b477 [D3D12] Remove unnecessary binding count uint32_t casts 2022-05-17 21:33:17 +03:00
Triang3l 5f2b0a899a [Vulkan] Fix TransientDescriptorPool ignoring the descriptor type 2022-05-15 22:20:24 +03:00
Triang3l f9261811a9 [D3D12] Fix layouts_mutex_ lock naming 2022-05-15 18:52:28 +03:00
Triang3l 0db94a700f [Vulkan] Use pipeline layout key structures directly 2022-05-15 17:42:27 +03:00
Triang3l b80361ee3c [Vulkan] Texture cache: Maximum dimensions, null images 2022-05-15 16:59:27 +03:00
Triang3l 185c23dd50 [Vulkan] Gather shader stages that VS can be translated into 2022-05-15 16:31:24 +03:00
Triang3l 7d19a8c0e8 [Vulkan] Add missing <functional> include for std::hash 2022-05-15 16:20:12 +03:00
Triang3l 862c457761 [Vulkan] Use Shader::IsHostVertexShaderTypeDomain 2022-05-15 16:19:36 +03:00
Triang3l 05adfbc58d Merge branch 'master' into vulkan 2022-05-15 16:18:41 +03:00
Triang3l a65fd4f673 [GPU] Shader::IsHostVertexShaderTypeDomain 2022-05-15 16:13:05 +03:00
Triang3l f9b3b90a68 [D3D12] Subsystem management order cleanup 2022-05-14 22:30:06 +03:00
Triang3l 60052fb4fc [Vulkan] Don't require imageViewFormatSwizzle in the immediate drawer 2022-05-14 22:18:21 +03:00
Triang3l d6a9056952 [D3D12] D3D12Texture::SRVDescriptorKey structure 2022-05-14 18:41:15 +03:00
Triang3l 26cf717394 [GPU] Make TextureCache constructors explicit 2022-05-14 18:28:32 +03:00
Triang3l 775b4623dc Merge branch 'master' into vulkan 2022-05-14 17:05:39 +03:00
Triang3l d280b3953d [GPU] Texture object/binding management to common superclass 2022-05-14 16:18:10 +03:00
Triang3l af3158f1bf [Legacy Vulkan] Add Vulkan prefix to Pipeline/TextureCache to avoid future name collisions 2022-05-11 21:21:33 +03:00
Triang3l 73d574a046 [Vulkan] Rectangle and quad list geometry shader generation 2022-05-10 21:48:18 +03:00
Triang3l b9256fcdbd Merge branch 'master' into vulkan 2022-05-10 15:57:50 +03:00
Triang3l e6fb9883d2 [D3D12] Discard primitives with NaN position in GS 2022-05-09 22:34:17 +03:00
Triang3l 4cd4a91aa7 [D3D12] Rectangle GS comment typo fix [ci skip] 2022-05-09 19:17:55 +03:00
Triang3l 8f0e751909 [D3D12] Runtime geometry shader generation 2022-05-09 19:16:22 +03:00
Triang3l 44cda56d35 [GPU] Handle kRegisters and kGammaRamp in the trace viewer 2022-05-08 19:41:11 +03:00
Triang3l 2473496c7e [GPU] Make RegisterFile::kRegisterCount constexpr 2022-05-08 19:37:29 +03:00
Triang3l 72cf75f365 [DXBC] Geometry shader instructions 2022-05-07 22:11:31 +03:00
Caroline Joy Bell d36c3975d8 [UI] Implement Type::kDirectory in Win32FilePicker 2022-05-07 21:54:26 +03:00
Triang3l e3425b242e [DXBC] Both v[#] and v[#][#] operands for HS and GS 2022-05-07 16:17:17 +03:00
Gliniak c65f240c0b [Kernel] Improved TUs Support
- Changed name of config option to apply_title_update to better reflect what that option does
- Mount TU package to UPDATE: partition
- Simplified UserModule::title_id()
- Splitted loading module into two parts to allow applying TUs and custom patches
2022-05-06 08:04:47 +02:00
Triang3l 5875f6ab31 [UI] Windows: Disable rounded corners 2022-05-05 21:46:20 +03:00
Triang3l 9c8e0cc53e [GPU] DC_LUT_PWL_DATA comment fix [ci skip] 2022-05-05 13:13:30 +03:00
Triang3l c794d0d538 [GPU] DC_LUT_RW_INDEX/WRITE_EN_MASK + gamma ramp and registers in traces 2022-05-05 13:10:29 +03:00
Triang3l 2d90d5940f [DXBC] Jump to the loop skip address before pushing 2022-05-04 22:01:30 +03:00
Triang3l 0e0f04dc1d [D3D12] Fix point size calculation + point code cleanup
6fcf9d21fe made per-vertex diameter vs. constant radius consistent, and with that commit the shader works with direct pixel to NDC conversion, however, the NDC conversion factor was outdated in that commit (still included the 0.5 factor for diameter to radius conversion, resulting in all points being 50% narrower along each axis than needed). Now, the diameter to radius conversion factor is used there properly, and also the multiplication of the per-vertex diameter by 0.5 has been removed from the shader since the constant already includes it now (the constant diameter is passed via the system constants instead of the radius also).
2022-05-04 13:26:30 +03:00
Peter Wright 7ab5ccbbd9 Add #include <cfloat> to fix build error on Linux. 2022-05-03 19:45:10 +03:00
Triang3l 9e6f96a2fc Merge branch 'master' into vulkan 2022-05-03 16:21:30 +03:00
Triang3l 6fcf9d21fe [D3D12] Point sprite size fixes, point/line bits in PsParamGen 2022-05-03 16:15:16 +03:00
Triang3l fe50c5c2e5 [XeSL] Prefix all local names with `xesl_id/var_` 2022-05-03 13:48:32 +03:00
Triang3l 72a4d14056 Merge branch 'master' into vulkan 2022-05-03 00:13:31 +03:00
Triang3l b88f715140 Merge branch 'master' into vulkan 2022-05-03 00:13:17 +03:00
Triang3l 7a89ad16a6 [D3D12] Update D3D12RenderTargetCache::Update write mask argument name 2022-05-02 23:16:18 +03:00
Gliniak ccbb5a2ebf Cleanup 2022-04-30 11:45:22 +02:00
Gliniak d78fd19ab4 Fixed incorrect hash generation + lint fixes 2022-04-29 20:33:21 +02:00
Gliniak 585b208fc0 Added support for multiple game hashes 2022-04-29 09:41:45 +02:00
Triang3l 0fd578cafd [GPU] Get unclipped draw height by running VS on the CPU 2022-04-28 22:25:25 +03:00
Triang3l b2b1d7b518 [GPU] More accurate vertex kill + PsParamGen/point documentation 2022-04-27 23:10:56 +03:00
Triang3l 5ec0c92601 [GPU] Ignore z_enable for !z_write_enable && z_func == ALWAYS 2022-04-27 21:46:29 +03:00
Triang3l 5519dbb39f [GPU] Shader control flow documentation improvements 2022-04-27 21:34:08 +03:00
Triang3l b42680abf7 [GPU] Shader ALU refactoring + documentation
Mainly move instruction info from the ShaderTranslator to xe::gpu::ucode for future use in the CPU shader interpreter
2022-04-27 20:52:20 +03:00
Gliniak fc16e3dc40 Support for patch types:
- float
 - double
 - string
 - u16string
 - byte_array

Plus some smaller changes
2022-04-27 09:41:29 +02:00
Triang3l df9a37f798 [GPU] Ucode disasm: Fix exec formatting 2022-04-26 23:08:31 +03:00
Triang3l 69958cba9d [GPU] shader-compiler: Accept little-endian ucode 2022-04-26 22:59:02 +03:00
Triang3l 443d61c9e1 [D3D12] GetFormatCopyInfo: Remove unused divide_by_block_size variable 2022-04-26 22:42:17 +03:00
Triang3l fcf6a7ded1 [Android] Minor postInvalidateWindowSurface JNI cleanup 2022-04-26 22:41:11 +03:00
Triang3l 12ff951972 [Base] More flexible Xenos float16 conversion functions 2022-04-26 22:35:37 +03:00
Joel Linn e3dd873892 [Base] Fix wait for callback return
- If wait item has disarmed itself and is then disarmed by another
  thread, still wait for the callback to return to meet guaratees
2022-04-26 13:56:11 -05:00
Joel Linn 3b4dc7da3b [Base] Use disruptorplus spin wait
- Attempt to fix deadlocks when using valgrind on CI
2022-04-26 13:56:11 -05:00
Joel Linn e59a0e1206 [Base] Relax some timing constraints.
- Because setting the timer is scheduled by us but the wait on POSIX is
  currently scheduled by pthreads, this solves issues on overprovisioned
  CIs
2022-04-26 13:56:11 -05:00
Joel Linn 4a36a7962c [Base] Remove unneeded delay scheduler 2022-04-26 13:56:11 -05:00
Joel Linn 15950eec37 [Base] Use chrono APIs for Timers 2022-04-26 13:56:11 -05:00
Joel Linn 1478be14c7 [Base] Add chrono tests 2022-04-26 13:56:11 -05:00
Joel Linn 23eef94984 [Base] Add chrono support
- WinSystemClock is a FILETIME clock without scaling, can convert to
  system_time
- XSystemClock is a FILTETIME clock with scaling applied, can only
  convert to WinSystemClock
2022-04-26 13:56:11 -05:00
Joel Linn 9b4168cce9 [Base] Make HighResolutionTimer platform agnostic 2022-04-26 13:56:11 -05:00
Joel Linn 75357caeaf [Base] Add TimerQueue
- Cross platform functionality similar to Windows' `CreateTimerQueue`
  with `WT_EXECUTEINTIMERTHREAD`
2022-04-26 13:56:11 -05:00
Joel Linn a85fc25040 [Base] Add more tests for HighResolutionTimer 2022-04-26 13:56:11 -05:00
Wunkolo be8b9c512f [x64] Add GFNI optimization for SPLAT(int8)
`pxor` is a zero-uop register-rename and `gf2p8affineqb dest, zero, int8`
is a very quick single-instruction way to use affine galois
transformations to fill a register with an immediate byte without
touching memory.
2022-04-26 13:46:46 -05:00
Gliniak c73cdb506a Initial support for xex patching 2022-04-26 13:26:49 +02:00
Gliniak 31eb639ade Added Premake Files For PatchingSystem 2022-04-26 13:26:49 +02:00
Gliniak 3a115ae6a0 [Kernel] Restored usage of: log_string_format_kernel_calls 2022-04-14 13:48:24 -05:00
Triang3l ef8a60e011 [GPU] Round tessellation patch vertex count up (by @deaklajos #2007)
Also move the clamping of the guest index count to the index buffer size to the place before it's read in calculations
2022-04-14 21:19:12 +03:00
Triang3l 38aca269e1 [GPU] Offset and clamp tessellation patch index (#2008, thanks @deaklajos) 2022-04-14 13:04:34 +03:00
Triang3l fea430f1f9 [GPU] Fix scalar c[#+aL], shader docs/refactoring 2022-04-13 23:08:19 +03:00
Triang3l 1f324bebcd [GPU] Norm16 > float16 texture load shaders 2022-04-09 23:34:50 +03:00
Triang3l 744767f549 [D3D12] Compile all built-in shaders with the same FXC version 2022-04-09 23:24:28 +03:00
Triang3l 72f3eead63 [GPU] Texture load shader style (alignment) cleanup 2022-04-09 23:23:54 +03:00
DESKTOP-F0UGBP9\deakl 8d02c5ab21 [GPU] Fixed size 0 point sprites enlarged to default 2022-04-05 02:25:24 +03:00
Triang3l 47799163bd Merge branch 'master' into vulkan 2022-04-04 22:02:46 +03:00
Triang3l 3d48fde5ca [GPU] XeSL texture load shaders + minor XeSL cleanup 2022-04-04 21:48:27 +03:00
Triang3l 0acb97d383 [Vulkan] EDRAM range ownership transfers, resolve clears, 2x-as-4x MSAA
Transfers are functional on a D3D12-like level, but need additional work so fallbacks are used when multisampled integer sampled images are not supported, and to eliminate transfers between render targets within Vulkan format compatibility classes by using different views directly.
2022-04-03 16:40:29 +03:00
Triang3l 85fc7036b8 Merge branch 'master' into vulkan 2022-04-02 22:45:23 +03:00
Triang3l c4eae232f1 [D3D12] Fixes/cleanup for render targets and barriers 2022-04-02 22:44:10 +03:00
Triang3l 1131dff705 Merge branch 'master' into vulkan 2022-03-28 21:58:34 +03:00
Triang3l 0f3207d019 [Vulkan] Fix basePipelineIndex signedness 2022-03-28 21:57:44 +03:00