Commit Graph

6270 Commits

Author SHA1 Message Date
zilmar a2c4e06f90 Android: Get rid of usage of project64_data directory 2023-10-26 11:14:47 +10:30
zilmar bf480623bd [Android] Add Android/Bridge to clang checking 2023-10-26 11:05:20 +10:30
zilmar ebdef8bbdb Android: remove InterpreterCPU.cpp from CMakeLists.txt 2023-10-19 20:19:57 +10:30
zilmar 8f062975c3 Core: improve DisplayControlRegHandler::Write32 2023-10-19 19:28:38 +10:30
zilmar d6a2ae80c1 Core: Remove SystemRegisters 2023-10-19 14:56:53 +10:30
zilmar d58168bcb9 Core: R4300iOp access the registers directly, not through CSystemRegisters 2023-10-19 12:52:33 +10:30
zilmar 4d78f56aa2 Core: In R4300iOp have a member variable for system, reg, mmu 2023-10-19 12:31:26 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 7f42f70283 Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static 2023-10-19 10:28:25 +10:30
zilmar d3edbf6dda Core: move CInterpreterCPU into R4300iOp 2023-10-19 09:32:42 +10:30
zilmar d4dbc5a3f4 Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio 2023-10-14 11:53:35 +10:30
zilmar 00c5057b17 Core: Make sure precision is correct for COP1_D_SQRT 2023-10-13 00:16:14 +10:30
zilmar 3a68d3d92a Core: LL/LLD store address 2023-10-12 19:55:29 +10:30
zilmar a6405cfa2d Core: Add masking around DPC_START_REG/DPC_END_REG 2023-10-12 17:50:58 +10:30
zilmar 4e71221147 Core: Fix up FPU mode register location 2023-10-12 14:53:44 +10:30
zilmar befa57924d Core: Fix clang compile issues 2023-10-05 15:01:09 +10:30
zilmar f73c3708a5 Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty 2023-10-05 14:45:17 +10:30
zilmar e74e8f6a23 Core: Have load/store ops be able to use 64bit addresses 2023-10-05 14:28:32 +10:30
zilmar 9f07fe2aac Core: Get tlb addresses to be 64bit 2023-10-05 13:42:31 +10:30
zilmar 4b844495b7 Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
2023-10-05 13:10:45 +10:30
zilmar 35105e814e Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss 2023-10-05 09:54:41 +10:30
zilmar b7311cc611 Core: Change Non memory load/store to not use tlb 2023-10-05 09:32:45 +10:30
zilmar a975af0e3c Rsp: only use alignas for Visual Studio 2023-09-28 16:18:39 +09:30
zilmar dd7ec63dd9 Rsp: Change usage of alignas to try and fix android build 2023-09-28 15:53:46 +09:30
zilmar 7e249d22b1 Try to fix android build 2023-09-28 15:25:34 +09:30
zilmar 46e6e54f24 RSP: improve running RSP multithreaded 2023-09-28 14:46:36 +09:30
zilmar 15e6e460d2 Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH 2023-09-28 13:39:23 +09:30
zilmar 3c52d8e2e3 RSP: use vt instead of rt when using RSP_Vect 2023-09-28 11:57:29 +09:30
zilmar 0bd6a96118 RSP: fix display of VRCP instruction 2023-09-28 11:54:50 +09:30
zilmar b1240072c6 RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core 2023-09-28 11:53:57 +09:30
zilmar ac3e0f83d1 Rsp: Use RSP Register Handler 2023-09-28 11:52:06 +09:30
zilmar bd1ec4ff0f Core: Create a setting for RDRAM Size that plugins can read 2023-09-28 07:29:11 +09:30
zilmar 99417fc5d9 Core: reset run event in CRSP_Plugin after rom close 2023-09-28 07:19:20 +09:30
zilmar f817becf9c Core: Create a handler for RSP registers that is accessible to the core and the RSP 2023-09-28 07:03:01 +09:30
zilmar 03e13455f9 Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot 2023-09-28 06:39:39 +09:30
zilmar 2caa457d02 Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
2023-09-22 11:01:46 +09:30
zilmar 10d2b77d7c Core: Try to fix android build 2023-09-21 20:13:41 +09:30
zilmar aadcca7528 Core: Fix clang issue 2023-09-21 18:40:27 +09:30
zilmar 6307888be4 Core: fix up exception generator functions 2023-09-21 18:07:56 +09:30
zilmar 32ff820a03 RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH) 2023-09-21 15:51:16 +09:30
zilmar dc95d2f7a4 RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR) 2023-09-21 15:44:07 +09:30
zilmar 174e751a4a RSP: Fix up load ops (LUV, LHV, LFV, LTV) 2023-09-21 15:30:07 +09:30
zilmar bdaf8cf78c RSP: Clean up store vector ops (SHV, SFV, STV, SWV) 2023-09-21 15:25:45 +09:30
zilmar 5dcc7e200f Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core 2023-09-21 15:16:26 +09:30
zilmar 42a944c660 RSP: Setup option to run in a thread 2023-09-21 14:25:07 +09:30
zilmar c4abebe201 Core: Update <Project64-plugin-spec\ to <Project64-plugin-spec/ 2023-09-21 14:13:08 +09:30
zilmar f3d6d3fc7c Core: for tlb miss only use special address when address is not defined 2023-09-14 18:39:15 +09:30
zilmar e0c125e837 Core: Fix clang issue 2023-09-14 16:33:20 +09:30
zilmar c02858c7a0 Core: Add LLD opcode 2023-09-14 16:31:37 +09:30
zilmar f559aed2ad Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function 2023-09-14 16:23:26 +09:30