zilmar
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4b844495b7
|
Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
|
2023-10-05 13:10:45 +10:30 |
|
zilmar
|
35105e814e
|
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
|
2023-10-05 09:54:41 +10:30 |
|
zilmar
|
b7311cc611
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Core: Change Non memory load/store to not use tlb
|
2023-10-05 09:32:45 +10:30 |
|
zilmar
|
a975af0e3c
|
Rsp: only use alignas for Visual Studio
|
2023-09-28 16:18:39 +09:30 |
|
zilmar
|
dd7ec63dd9
|
Rsp: Change usage of alignas to try and fix android build
|
2023-09-28 15:53:46 +09:30 |
|
zilmar
|
7e249d22b1
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Try to fix android build
|
2023-09-28 15:25:34 +09:30 |
|
zilmar
|
46e6e54f24
|
RSP: improve running RSP multithreaded
|
2023-09-28 14:46:36 +09:30 |
|
zilmar
|
15e6e460d2
|
Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH
|
2023-09-28 13:39:23 +09:30 |
|
zilmar
|
3c52d8e2e3
|
RSP: use vt instead of rt when using RSP_Vect
|
2023-09-28 11:57:29 +09:30 |
|
zilmar
|
0bd6a96118
|
RSP: fix display of VRCP instruction
|
2023-09-28 11:54:50 +09:30 |
|
zilmar
|
b1240072c6
|
RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core
|
2023-09-28 11:53:57 +09:30 |
|
zilmar
|
ac3e0f83d1
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Rsp: Use RSP Register Handler
|
2023-09-28 11:52:06 +09:30 |
|
zilmar
|
bd1ec4ff0f
|
Core: Create a setting for RDRAM Size that plugins can read
|
2023-09-28 07:29:11 +09:30 |
|
zilmar
|
99417fc5d9
|
Core: reset run event in CRSP_Plugin after rom close
|
2023-09-28 07:19:20 +09:30 |
|
zilmar
|
f817becf9c
|
Core: Create a handler for RSP registers that is accessible to the core and the RSP
|
2023-09-28 07:03:01 +09:30 |
|
zilmar
|
03e13455f9
|
Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot
|
2023-09-28 06:39:39 +09:30 |
|
zilmar
|
2caa457d02
|
Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
|
2023-09-22 11:01:46 +09:30 |
|
zilmar
|
10d2b77d7c
|
Core: Try to fix android build
|
2023-09-21 20:13:41 +09:30 |
|
zilmar
|
aadcca7528
|
Core: Fix clang issue
|
2023-09-21 18:40:27 +09:30 |
|
zilmar
|
6307888be4
|
Core: fix up exception generator functions
|
2023-09-21 18:07:56 +09:30 |
|
zilmar
|
32ff820a03
|
RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH)
|
2023-09-21 15:51:16 +09:30 |
|
zilmar
|
dc95d2f7a4
|
RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR)
|
2023-09-21 15:44:07 +09:30 |
|
zilmar
|
174e751a4a
|
RSP: Fix up load ops (LUV, LHV, LFV, LTV)
|
2023-09-21 15:30:07 +09:30 |
|
zilmar
|
bdaf8cf78c
|
RSP: Clean up store vector ops (SHV, SFV, STV, SWV)
|
2023-09-21 15:25:45 +09:30 |
|
zilmar
|
5dcc7e200f
|
Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core
|
2023-09-21 15:16:26 +09:30 |
|
zilmar
|
42a944c660
|
RSP: Setup option to run in a thread
|
2023-09-21 14:25:07 +09:30 |
|
zilmar
|
c4abebe201
|
Core: Update <Project64-plugin-spec\ to <Project64-plugin-spec/
|
2023-09-21 14:13:08 +09:30 |
|
zilmar
|
f3d6d3fc7c
|
Core: for tlb miss only use special address when address is not defined
|
2023-09-14 18:39:15 +09:30 |
|
zilmar
|
e0c125e837
|
Core: Fix clang issue
|
2023-09-14 16:33:20 +09:30 |
|
zilmar
|
c02858c7a0
|
Core: Add LLD opcode
|
2023-09-14 16:31:37 +09:30 |
|
zilmar
|
f559aed2ad
|
Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
|
2023-09-14 16:23:26 +09:30 |
|
zilmar
|
ae4af8746b
|
Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
|
2023-09-14 13:09:11 +09:30 |
|
zilmar
|
8b14b6d7d1
|
Core: Move InitRegisters to register class
|
2023-09-14 12:01:16 +09:30 |
|
zilmar
|
a5a4873e84
|
Core: Have CRegisters::DoAddressError to not directly modify program counter
|
2023-09-14 11:37:21 +09:30 |
|
zilmar
|
2d09178449
|
Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions
|
2023-09-14 11:15:42 +09:30 |
|
zilmar
|
5da5dab3c5
|
Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
|
2023-09-14 11:09:28 +09:30 |
|
zilmar
|
fcd7257adc
|
Core: Change COP0 Status register to a struct breaking up the bits
|
2023-09-14 10:23:36 +09:30 |
|
zilmar
|
9ffd87168a
|
Core: DisplayControlRegHandler::Read32 read more of the registers
|
2023-09-14 09:40:11 +09:30 |
|
zilmar
|
002f2e17c3
|
RSP: Clean up code for vector multiple ops
|
2023-09-07 11:54:36 +09:30 |
|
zilmar
|
4e9a692449
|
RSP: Add RSP_Vector_VRNDP
|
2023-09-07 11:41:17 +09:30 |
|
zilmar
|
0cadbe0f70
|
RSP: Add clamp16
|
2023-09-07 11:31:31 +09:30 |
|
zilmar
|
af1c0c2b55
|
RSP: Add Vmulq
|
2023-09-07 11:30:15 +09:30 |
|
zilmar
|
d468b863c2
|
Rsp: add vnop for vnull
|
2023-09-07 11:29:16 +09:30 |
|
zilmar
|
8b71ef3bc1
|
RSP: Add RSP_Vector_Reserved
|
2023-09-07 11:23:35 +09:30 |
|
zilmar
|
ab67374c8a
|
RSP: Update the display of RSP opcodes in debugger
|
2023-09-07 11:19:44 +09:30 |
|
zilmar
|
4f74dc4bb0
|
Rsp: Update display of vector in debugger
|
2023-09-07 11:17:08 +09:30 |
|
zilmar
|
ab03916a70
|
Core: let the stack pointer equal end of rdram
|
2023-09-07 11:13:54 +09:30 |
|
zilmar
|
7199096748
|
Core: Merge CheckFPUException into CheckFPUResult64
|
2023-08-31 18:52:34 +09:30 |
|
zilmar
|
91d1c6e237
|
Core: Add fpu exceptions to COP1_S_MUL
|
2023-08-31 11:09:48 +09:30 |
|
zilmar
|
2f7a35613f
|
Core: Add exception to COP1_S_SUB
|
2023-08-31 10:54:41 +09:30 |