Commit Graph

6351 Commits

Author SHA1 Message Date
zilmar 97ec1f533b Core: Make sure precision is set to 53bit 2024-03-07 20:52:24 +10:30
zilmar 290040d945 Merge branch 'develop' of https://github.com/project64/project64 into develop 2024-02-29 16:07:32 +10:30
zilmar 190c408019 Core: Fix clang formatting in x86/x86RecompilerOps.cpp 2024-02-29 16:06:56 +10:30
Derek "Turtle" Roe 565d45de8a
Update minimum requirements for Project64 (#2409)
* Fix typo in support window

* Fix the typo for real

* Update minimum requirements

* Change minimum to supported
2024-02-29 15:18:28 +10:30
jeremie-78 1bde8589e9
Cheat (#2410)
* Update The Legend of Zelda - Majora's Mask (E) (M4) (V1.0).cht

Added Time control cheat

* Update The Legend of Zelda - Majora's Mask (E) (M4) (V1.1).cht

Added Time control

* Update The Legend of Zelda - Majora's Mask (U).cht

Added Time control cheat

* Update The Legend of Zelda - Majora's Mask - Collector's Edition (E) (GC Version).cht

Added Time control cheat

* Update The Legend of Zelda - Majora's Mask - Collector's Edition (U) (GC).cht

Added Time control cheat

* Update Zelda no Densetsu - Mujura no Kamen (J) (V1.0).cht

Added Time control cheat

* Update Zelda no Densetsu - Mujura no Kamen (J) (V1.1).cht

Added Time control cheat

* Update Zelda no Densetsu - Mujura no Kamen - Zelda Collection Version (J) (GC).cht

Added Time control cheat
2024-02-29 15:17:48 +10:30
zilmar f7aa6ef6cb Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions 2024-02-29 15:16:29 +10:30
zilmar 25dc3ed36f Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes 2024-02-29 15:13:14 +10:30
zilmar d2649f7a13 Core: Some clean up recompiler ops 2024-02-22 19:56:23 +10:30
zilmar fae0b81e21 Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register 2024-02-22 19:41:10 +10:30
zilmar e082cd55df Core: Get COP1_D_TRUNC_W to work in recompiler 2024-02-15 21:08:49 +10:30
zilmar 2559d23592 Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID 2024-02-15 21:02:27 +10:30
zilmar 46f6fae40f Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit 2024-02-15 21:00:12 +10:30
zilmar 2014237ed6 Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler 2024-02-08 19:34:14 +10:30
zilmar ad1a2a2d9a Core: Update neg.s for the recompiler 2024-02-01 18:17:03 +10:30
zilmar b6671adf5d Core: Update abs.s for recompiler 2024-02-01 18:15:33 +10:30
zilmar bc3fe0fe16 Core: Handle FP Status Reg being mapped better 2024-01-25 18:46:39 +10:30
zilmar 7707f9c7b2 Core: Fix up mov.s and mov.d for correct behaviour in the recompiler 2024-01-25 16:25:06 +10:30
zilmar 272144dc37 Core: check timer on cop1 unusable 2024-01-25 16:23:03 +10:30
zilmar f0f44c67f4 Core: Make mov.s the same as mov.d 2024-01-25 15:32:56 +10:30
zilmar 7ed94b653e Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions 2024-01-18 17:09:27 +10:30
zilmar 2231e8d6c0 Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64 2024-01-18 16:53:14 +10:30
zilmar 71067ccdc4 Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP 2024-01-11 18:17:05 +10:30
zilmar 5c56f9df83 RSP: Update the size of the skip in the length for DMA 2024-01-11 17:50:23 +10:30
zilmar 4dc3e35bb4 Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions 2024-01-04 16:51:11 +10:30
zilmar f8089f565e Core: Unmap FPU_Float with writing to m_FPR_UDW 2024-01-04 14:40:42 +10:30
zilmar 552b8f744a Core: update Format_Name to match FPU_STATE 2024-01-04 13:11:21 +10:30
zilmar 6ca8333d39 Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions 2024-01-04 12:39:51 +10:30
zilmar c9d2bbd221 Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped 2024-01-04 12:37:06 +10:30
zilmar 0998f0ff0e Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer 2024-01-04 12:32:55 +10:30
zilmar 23cff4d7c5 Core: Add x86 asm opcode Jnp 2024-01-04 12:31:26 +10:30
zilmar 91a8a828d7 Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW 2024-01-04 12:01:21 +10:30
zilmar 320769d991 Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr 2024-01-04 10:33:07 +10:30
zilmar dafa1fb24d Core: Have COP1_W_CVT_S handle the initialization of exceptions 2023-12-28 11:19:06 +10:30
zilmar 17288c90c0 Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32 2023-12-28 10:23:18 +10:30
zilmar e2306e3541 Core: Get COP1_S_CVT_W to handle inexact 2023-12-28 09:21:53 +10:30
zilmar 8399fdb893 Core: Clear the Divide-by-zero flag 2023-12-21 21:24:33 +10:30
zilmar d14a639a62 Core: Implement COP1_S_DIV with fpu exceptions 2023-12-21 14:11:29 +10:30
zilmar 8e54ec8c8e Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis 2023-12-21 14:10:21 +10:30
zilmar b263ee10b0 Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0 2023-12-21 10:41:16 +10:30
zilmar 1810bfda5c Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops 2023-12-21 10:38:49 +10:30
zilmar 2c1610cfe2 Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode 2023-12-21 10:37:27 +10:30
zilmar 6610ae3058 Core: Have R4300iInstruction in CRecompilerOpsBase 2023-12-21 10:34:03 +10:30
zilmar 8e3fb3e302 Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference 2023-12-21 10:26:10 +10:30
zilmar c8e73ba18e Core: Handle unaligned SW exception in the recompiler 2023-12-14 23:04:26 +10:30
zilmar 972943cff7 Core: Allow LW to R0 be able to generate an exception 2023-12-14 17:21:52 +10:30
zilmar 89a6eaf9d1 Core: Add RecordLLAddress for 32bit register pointer 2023-12-14 13:52:15 +10:30
zilmar 67f5e4f854 Core: in LL for recompiler handle storing the address in COP[17] 2023-12-14 13:10:20 +10:30
zilmar d5a5f4cdac Core: Have Store Instruc rdb and user rdb matching 2023-12-14 12:21:03 +10:30
zilmar 5fec3f8d31 Core: remove the global of g_TLB 2023-12-14 12:09:24 +10:30
zilmar c67f3f0e97 Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it 2023-12-14 11:18:07 +10:30