zilmar
|
de1288bdca
|
Core: remove try/catch around Interpreter cpu
|
2023-11-30 21:15:14 +10:30 |
|
zilmar
|
df56964c96
|
Android: Remove unneeded log call
|
2023-11-30 21:13:27 +10:30 |
|
zilmar
|
5671f2b759
|
Android: Update how Addu cause android studio was not sign extending result
|
2023-11-30 21:12:53 +10:30 |
|
Derek "Turtle" Roe
|
acbb8f85a8
|
Fix typo in support window code (#2395)
* Fix typo in support window
* Fix the typo for real
|
2023-11-23 22:54:19 +10:30 |
|
zilmar
|
01673dac8d
|
Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
|
2023-11-23 14:20:48 +10:30 |
|
zilmar
|
d47b49d4b5
|
Core: Fix clang issue
|
2023-11-16 18:24:47 +10:30 |
|
zilmar
|
542afc4514
|
Core: remove some accidental added debug code
|
2023-11-16 18:16:35 +10:30 |
|
zilmar
|
ee714e2462
|
Core: On unmap base addresses reset to the correct address
|
2023-11-16 18:14:15 +10:30 |
|
zilmar
|
8f4f434820
|
Core: Get Fast tlb to just be 32bit
|
2023-11-16 17:11:05 +10:30 |
|
zilmar
|
dcb6969067
|
Core: Have entryHI use functions to set/get parts
|
2023-11-16 09:19:24 +10:30 |
|
zilmar
|
a0130ff896
|
Core: Convert %I64U to %llx
|
2023-11-16 09:03:32 +10:30 |
|
zilmar
|
e46ffde6b3
|
fix clang formatting
|
2023-11-09 12:59:40 +10:30 |
|
zilmar
|
296b7cf1cf
|
Android: Force RSP to be interpret
|
2023-11-09 12:45:36 +10:30 |
|
zilmar
|
0c8b10bbc7
|
Android: Get RSP core to compile on android
|
2023-11-09 11:53:06 +10:30 |
|
zilmar
|
09cc3442a2
|
Android: fix compile bug
|
2023-11-02 20:27:38 +10:30 |
|
zilmar
|
6fbc5c0264
|
Android: Move hle audio code in to main rsp plugin
|
2023-11-02 20:06:58 +10:30 |
|
zilmar
|
e6edbc6c82
|
Fix clang formatting
|
2023-10-27 10:14:21 +10:30 |
|
zilmar
|
4770d29ec0
|
Core: Get system events to be internal not global
|
2023-10-26 19:59:11 +10:30 |
|
zilmar
|
d3f4132770
|
Android: When listing a rom not in rdb, use game file instead
|
2023-10-26 11:18:24 +10:30 |
|
zilmar
|
b74e21d056
|
Android: Show base dir to splash logs when starting
|
2023-10-26 11:17:49 +10:30 |
|
zilmar
|
bf480623bd
|
[Android] Add Android/Bridge to clang checking
|
2023-10-26 11:05:20 +10:30 |
|
zilmar
|
8f062975c3
|
Core: improve DisplayControlRegHandler::Write32
|
2023-10-19 19:28:38 +10:30 |
|
zilmar
|
d6a2ae80c1
|
Core: Remove SystemRegisters
|
2023-10-19 14:56:53 +10:30 |
|
zilmar
|
d58168bcb9
|
Core: R4300iOp access the registers directly, not through CSystemRegisters
|
2023-10-19 12:52:33 +10:30 |
|
zilmar
|
4d78f56aa2
|
Core: In R4300iOp have a member variable for system, reg, mmu
|
2023-10-19 12:31:26 +10:30 |
|
zilmar
|
ae0097550f
|
Core: Make R4300iOp opcodes not static
|
2023-10-19 11:43:32 +10:30 |
|
zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
d3edbf6dda
|
Core: move CInterpreterCPU into R4300iOp
|
2023-10-19 09:32:42 +10:30 |
|
zilmar
|
d4dbc5a3f4
|
Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
|
2023-10-14 11:53:35 +10:30 |
|
zilmar
|
00c5057b17
|
Core: Make sure precision is correct for COP1_D_SQRT
|
2023-10-13 00:16:14 +10:30 |
|
zilmar
|
3a68d3d92a
|
Core: LL/LLD store address
|
2023-10-12 19:55:29 +10:30 |
|
zilmar
|
a6405cfa2d
|
Core: Add masking around DPC_START_REG/DPC_END_REG
|
2023-10-12 17:50:58 +10:30 |
|
zilmar
|
4e71221147
|
Core: Fix up FPU mode register location
|
2023-10-12 14:53:44 +10:30 |
|
zilmar
|
befa57924d
|
Core: Fix clang compile issues
|
2023-10-05 15:01:09 +10:30 |
|
zilmar
|
f73c3708a5
|
Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
|
2023-10-05 14:45:17 +10:30 |
|
zilmar
|
e74e8f6a23
|
Core: Have load/store ops be able to use 64bit addresses
|
2023-10-05 14:28:32 +10:30 |
|
zilmar
|
9f07fe2aac
|
Core: Get tlb addresses to be 64bit
|
2023-10-05 13:42:31 +10:30 |
|
zilmar
|
4b844495b7
|
Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
|
2023-10-05 13:10:45 +10:30 |
|
zilmar
|
35105e814e
|
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
|
2023-10-05 09:54:41 +10:30 |
|
zilmar
|
b7311cc611
|
Core: Change Non memory load/store to not use tlb
|
2023-10-05 09:32:45 +10:30 |
|
zilmar
|
a975af0e3c
|
Rsp: only use alignas for Visual Studio
|
2023-09-28 16:18:39 +09:30 |
|
zilmar
|
dd7ec63dd9
|
Rsp: Change usage of alignas to try and fix android build
|
2023-09-28 15:53:46 +09:30 |
|
zilmar
|
7e249d22b1
|
Try to fix android build
|
2023-09-28 15:25:34 +09:30 |
|
zilmar
|
46e6e54f24
|
RSP: improve running RSP multithreaded
|
2023-09-28 14:46:36 +09:30 |
|
zilmar
|
15e6e460d2
|
Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH
|
2023-09-28 13:39:23 +09:30 |
|
zilmar
|
3c52d8e2e3
|
RSP: use vt instead of rt when using RSP_Vect
|
2023-09-28 11:57:29 +09:30 |
|
zilmar
|
0bd6a96118
|
RSP: fix display of VRCP instruction
|
2023-09-28 11:54:50 +09:30 |
|
zilmar
|
b1240072c6
|
RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core
|
2023-09-28 11:53:57 +09:30 |
|
zilmar
|
ac3e0f83d1
|
Rsp: Use RSP Register Handler
|
2023-09-28 11:52:06 +09:30 |
|
zilmar
|
bd1ec4ff0f
|
Core: Create a setting for RDRAM Size that plugins can read
|
2023-09-28 07:29:11 +09:30 |