* Fixed V2/V3 unpacks to behave same as the SSE unpacks (matches undefined PS2 behaviors)
* Removed legacy vifUnpacker (haven't needed it for any regression testing in forever).
* Move some VIF MARK console spam to DevCon (Ape Escape 3)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3746 96395faa-99c1-11dd-bbfe-3dabce05a288
* Both INTC and DMAC exceptions are now issued together when possible (0x400 | 0x800 to the CAUSE register, respectively)
* CPU exceptions are checked on every event now, instead of using scheduled interrupts on bits 30/31. This removes the need to constantly reschedule events during interrupt-disabled states.
* CPU exception test is moved to the top of the EE event test.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3728 96395faa-99c1-11dd-bbfe-3dabce05a288
* remove personal rule target: has not worked since last change...
* Some fix to control. Update package std version
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3721 96395faa-99c1-11dd-bbfe-3dabce05a288
* Remove need for packed structs through use of unions.
* Streamlined the microBlockManager's linked list (less heap allocs and simpler interations).
* Use two 32 bit compares for fast block compares, instead of 6-7 individual u8 compares.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3717 96395faa-99c1-11dd-bbfe-3dabce05a288
- Code refactoring (mostly changing macros to functions/constants...)
- Made it so the disable-regAlloc option flushes every 32bit instruction, instead of every 64bit instruction (upper+lower instruction pair)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3713 96395faa-99c1-11dd-bbfe-3dabce05a288
int src; if (src < 0xffff8000) {}
so solution is either use (int)0xffff8000 or -0x8000...
it also doesn't seem to print out warnings about this either D:
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3712 96395faa-99c1-11dd-bbfe-3dabce05a288
* Writes via 16 and 8 bit ops now use 32-bit read/modify/write operations by default; which should enable nearly complete support for all such operations (instead of the formerly spotty coverage before).
* Eliminated almost all former 8/16-bit specific register operations. All code shares the same 32 bit handlers now.
* Completely revamped the developer trace logs for hardware registers! *ALL* registers are logged now, complete with address, name, and value being read/written (and nicely formatted!).
* Handlers are now fully page-based using templated functions (minor speedup)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3704 96395faa-99c1-11dd-bbfe-3dabce05a288
* Added ToString methods to the u128 type.
* Bugfixes for the FastFormat string utilities, namely when writing UTF8 content via the UTF16 formatter.
* MSVC: Removed obsolete disabling of unsigned/signed mismatch warning (4018)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3703 96395faa-99c1-11dd-bbfe-3dabce05a288
Spu2x: Use a standard destructor (POD safe stuff). Fix various segmentation faults (Issue 846)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3702 96395faa-99c1-11dd-bbfe-3dabce05a288
The dst param was never being modified since it was being passed by value instead of by reference. This leads me to believe the rest of MMI.cpp is probably riddled with errors too.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3698 96395faa-99c1-11dd-bbfe-3dabce05a288
Another round of configuration dialog renovations.
Fixes the leftover "Skipdraw" text when hacks are disabled.
Group the options a bit nicer. Group hardware Anti Aliasing with hacks.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3693 96395faa-99c1-11dd-bbfe-3dabce05a288
* Removed the hacky g_pVU1 pointer, which required VU1 cpu registers to be part of VU0. Replaced it with a standard VU1 variable (mimics all other CPU registers, which are standard static vars). We were using translation functions/tables for all VU0 memory operations anyway, so this was a no-brainer.
* Removed code from microVU that was only there to help deal with the fact that g_pVU1 was annoying.
* Turned eeMem->HW into a static global array eeHw [64k].
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3692 96395faa-99c1-11dd-bbfe-3dabce05a288
arcum42