mirror of https://github.com/PCSX2/pcsx2.git
Uninitialized variable fix in ScopedLock as found by Gregory, and a few more minor -> to . conversions.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3708 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -253,11 +253,13 @@ Threading::ScopedLock::~ScopedLock() throw()
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Threading::ScopedLock::ScopedLock( const Mutex* locker )
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{
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m_IsLocked = false;
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AssignAndLock( locker );
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}
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Threading::ScopedLock::ScopedLock( const Mutex& locker )
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{
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m_IsLocked = false;
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AssignAndLock( locker );
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}
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@ -268,6 +270,8 @@ void Threading::ScopedLock::AssignAndLock( const Mutex& locker )
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void Threading::ScopedLock::AssignAndLock( const Mutex* locker )
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{
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pxAssume(!m_IsLocked); // if we're already locked, changing the lock is bad mojo.
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m_lock = const_cast<Mutex*>(locker);
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if( !m_lock ) return;
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@ -111,8 +111,6 @@ static __fi void ZeroQWC( u128& dest )
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#define psSu64(mem) (*(u64 *)&eeMem->Scratch[(mem) & 0x3fff])
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#define psSu128(mem) (*(u128*)&eeMem->Scratch[(mem) & 0x3fff])
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#define psH_DMACh(mem) (*(DMACh*)&eeHw[(mem) & 0xffff])
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extern void memAlloc();
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extern void memReset(); // clears PS2 ram and loads the bios. Throws Exception::FileNotFound on error.
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extern void memShutdown();
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@ -25,9 +25,9 @@
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static bool QuickDmaExec( void (*func)(), u32 mem)
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{
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bool ret = false;
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DMACh *reg = &psH_DMACh(mem);
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DMACh& reg = (DMACh&)psHu32(mem);
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if (reg->chcr.STR && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
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if (reg.chcr.STR && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
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{
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func();
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ret = true;
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@ -56,11 +56,11 @@ static void StartQueuedDMA()
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static __ri void DmaExec( void (*func)(), u32 mem, u32 value )
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{
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DMACh *reg = &psH_DMACh(mem);
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DMACh& reg = (DMACh&)psHu32(mem);
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tDMA_CHCR chcr(value);
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//It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC
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if (reg->chcr.STR)
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if (reg.chcr.STR)
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{
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const uint channel = ChannelNumber(mem);
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@ -86,10 +86,10 @@ static __ri void DmaExec( void (*func)(), u32 mem, u32 value )
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}
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//Sanity Check for possible future bug fix0rs ;p
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//Spams on Persona 4 opening.
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//if(reg->chcr.TAG != chcr.TAG) DevCon.Warning(L"32bit CHCR Tag on %s changed to %x from %x QWC = %x Channel Active", ChcrName(mem), chcr.TAG, reg->chcr.TAG, reg->qwc);
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//if(reg.chcr.TAG != chcr.TAG) DevCon.Warning(L"32bit CHCR Tag on %s changed to %x from %x QWC = %x Channel Active", ChcrName(mem), chcr.TAG, reg.chcr.TAG, reg.qwc);
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//Here we update the LOWER CHCR, if a chain is stopped half way through, it can be manipulated in to a different mode
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//But we need to preserve the existing tag for now
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reg->chcr.set((reg->chcr.TAG << 16) | chcr.lower());
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reg.chcr.set((reg.chcr.TAG << 16) | chcr.lower());
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return;
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}
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else //Else the DMA is running (Not Suspended), so we cant touch it!
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@ -100,8 +100,8 @@ static __ri void DmaExec( void (*func)(), u32 mem, u32 value )
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if(chcr.STR == 0)
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{
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//DevCon.Warning(L"32bit Force Stopping %s (Current CHCR %x) while DMA active", ChcrName(mem), reg->chcr._u32, chcr._u32);
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reg->chcr.STR = 0;
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//DevCon.Warning(L"32bit Force Stopping %s (Current CHCR %x) while DMA active", ChcrName(mem), reg.chcr._u32, chcr._u32);
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reg.chcr.STR = 0;
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//We need to clear any existing DMA loops that are in progress else they will continue!
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if(channel == 1)
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@ -118,21 +118,21 @@ static __ri void DmaExec( void (*func)(), u32 mem, u32 value )
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cpuClearInt( channel );
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QueuedDMA._u16 &= ~(1 << channel); //Clear any queued DMA requests for this channel
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}
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//else DevCon.Warning(L"32bit Attempted to change %s CHCR (Currently %x) with %x while DMA active, ignoring QWC = %x", ChcrName(mem), reg->chcr._u32, chcr._u32, reg->qwc);
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//else DevCon.Warning(L"32bit Attempted to change %s CHCR (Currently %x) with %x while DMA active, ignoring QWC = %x", ChcrName(mem), reg.chcr._u32, chcr._u32, reg.qwc);
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return;
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}
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}
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//if(reg->chcr.TAG != chcr.TAG && chcr.MOD == CHAIN_MODE) DevCon.Warning(L"32bit CHCR Tag on %s changed to %x from %x QWC = %x Channel Not Active", ChcrName(mem), chcr.TAG, reg->chcr.TAG, reg->qwc);
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//if(reg.chcr.TAG != chcr.TAG && chcr.MOD == CHAIN_MODE) DevCon.Warning(L"32bit CHCR Tag on %s changed to %x from %x QWC = %x Channel Not Active", ChcrName(mem), chcr.TAG, reg.chcr.TAG, reg.qwc);
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reg->chcr.set(value);
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reg.chcr.set(value);
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if (reg->chcr.STR && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
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if (reg.chcr.STR && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
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{
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func();
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}
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else if(reg->chcr.STR)
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else if(reg.chcr.STR)
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{
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//DevCon.Warning(L"32bit %s DMA Start while DMAC Disabled\n", ChcrName(mem));
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QueuedDMA._u16 |= (1 << ChannelNumber(mem)); //Queue the DMA up to be started then the DMA's are Enabled and or the Suspend is lifted
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