mirror of https://github.com/PCSX2/pcsx2.git
Simplified CPU-level exception behavior:
* Both INTC and DMAC exceptions are now issued together when possible (0x400 | 0x800 to the CAUSE register, respectively) * CPU exceptions are checked on every event now, instead of using scheduled interrupts on bits 30/31. This removes the need to constantly reschedule events during interrupt-disabled states. * CPU exception test is moved to the top of the EE event test. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3728 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
02b390b0e1
commit
1698382065
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@ -20,9 +20,10 @@
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u32 s_iLastCOP0Cycle = 0;
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u32 s_iLastPERFCycle[2] = { 0, 0 };
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__ri void UpdateCP0Status() {
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//currently the 2 memory modes are not implemented. Given this function is called so much,
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//it's commented out for now. Only the interrupt test is needed. (rama)
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// Updates the CPU's mode of operation (either, Kernel, Supervisor, or User modes).
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// Currently the different modes are not implemented.
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// Given this function is called so much, it's commented out for now. (rama)
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__ri void cpuUpdateOperationMode() {
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//u32 value = cpuRegs.CP0.n.Status.val;
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@ -32,12 +33,12 @@ __ri void UpdateCP0Status() {
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//} else { // User Mode
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// memSetUserMode();
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//}
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cpuTestHwInts();
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}
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void __fastcall WriteCP0Status(u32 value) {
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cpuRegs.CP0.n.Status.val = value;
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UpdateCP0Status();
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cpuUpdateOperationMode();
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cpuSetNextBranchDelta(4);
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}
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void MapTLB(int i)
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@ -532,7 +533,8 @@ void ERET() {
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cpuRegs.pc = cpuRegs.CP0.n.EPC;
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cpuRegs.CP0.n.Status.b.EXL = 0;
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}
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UpdateCP0Status();
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cpuUpdateOperationMode();
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cpuSetNextBranchDelta(4);
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intSetBranch();
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}
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@ -540,7 +542,8 @@ void DI() {
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if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
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cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0)) {
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cpuRegs.CP0.n.Status.b.EIE = 0;
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//UpdateCP0Status(); // ints are disabled so checking for them is kinda silly...
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// IRQs are disabled so no need to do a cpu exception/event test...
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//cpuSetNextBranchDelta();
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}
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}
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@ -548,7 +551,8 @@ void EI() {
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if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
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cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0)) {
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cpuRegs.CP0.n.Status.b.EIE = 1;
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UpdateCP0Status();
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// schedule an event test, which will check for and raise pending IRQs.
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cpuSetNextBranchDelta(4);
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}
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}
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25
pcsx2/Hw.cpp
25
pcsx2/Hw.cpp
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@ -50,8 +50,7 @@ void hwReset()
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{
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hwInit();
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memzero_ptr<Ps2MemSize::Hardware>( eeHw );
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//memset(eeHw+0x2000, 0, 0x0000e000);
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memzero( eeHw );
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psHu32(SBUS_F260) = 0x1D000060;
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@ -73,16 +72,16 @@ void hwReset()
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ipuDmaReset();
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}
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__fi void intcInterrupt()
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__fi uint intcInterrupt()
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{
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if ((psHu32(INTC_STAT)) == 0) {
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//DevCon.Warning("*PCSX2*: intcInterrupt already cleared");
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return;
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return 0;
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}
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if ((psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0)
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{
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//DevCon.Warning("*PCSX2*: No valid interrupt INTC_MASK: %x INTC_STAT: %x", psHu32(INTC_MASK), psHu32(INTC_STAT));
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return;
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return 0;
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}
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HW_LOG("intcInterrupt %x", psHu32(INTC_STAT) & psHu32(INTC_MASK));
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@ -91,27 +90,29 @@ __fi void intcInterrupt()
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counters[1].hold = rcntRcount(1);
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}
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cpuException(0x400, cpuRegs.branch);
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//cpuException(0x400, cpuRegs.branch);
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return 0x400;
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}
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__fi void dmacInterrupt()
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__fi uint dmacInterrupt()
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{
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if( ((psHu16(DMAC_STAT + 2) & psHu16(DMAC_STAT)) == 0 ) &&
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( psHu16(DMAC_STAT) & 0x8000) == 0 )
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{
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//DevCon.Warning("No valid DMAC interrupt MASK %x STAT %x", psHu16(DMAC_STAT+2), psHu16(DMAC_STAT));
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return;
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return 0;
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}
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if (!(dmacRegs.ctrl.DMAE) || psHu8(DMAC_ENABLER+2) == 1)
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if (!dmacRegs.ctrl.DMAE || psHu8(DMAC_ENABLER+2) == 1)
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{
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//DevCon.Warning("DMAC Suspended or Disabled on interrupt");
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return;
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return 0;
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}
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HW_LOG("dmacInterrupt %x", (psHu16(DMAC_STAT + 2) & psHu16(DMAC_STAT) |
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psHu16(DMAC_STAT) & 0x8000));
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psHu16(DMAC_STAT) & 0x8000));
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cpuException(0x800, cpuRegs.branch);
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//cpuException(0x800, cpuRegs.branch);
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return 0x800;
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}
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void hwIntcIrq(int n)
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108
pcsx2/R5900.cpp
108
pcsx2/R5900.cpp
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@ -130,7 +130,7 @@ __ri void cpuException(u32 code, u32 bd)
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//Reset / NMI
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cpuRegs.pc = 0xBFC00000;
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Console.Warning("Reset request");
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UpdateCP0Status();
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cpuUpdateOperationMode();
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return;
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}
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else if((code & 0x38000) == 0x10000)
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@ -167,7 +167,7 @@ __ri void cpuException(u32 code, u32 bd)
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else
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cpuRegs.pc = 0xBFC00200 + offset;
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UpdateCP0Status();
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cpuUpdateOperationMode();
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}
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void cpuTlbMiss(u32 addr, u32 bd, u32 excode)
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@ -196,7 +196,7 @@ void cpuTlbMiss(u32 addr, u32 bd, u32 excode)
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}
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cpuRegs.CP0.n.Status.b.EXL = 1;
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UpdateCP0Status();
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cpuUpdateOperationMode();
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// Log=1; varLog|= 0x40000000;
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}
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@ -208,33 +208,6 @@ void cpuTlbMissW(u32 addr, u32 bd) {
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cpuTlbMiss(addr, bd, EXC_CODE_TLBS);
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}
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__fi void _cpuTestMissingINTC() {
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if (cpuRegs.CP0.n.Status.val & 0x400 &&
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psHu32(INTC_STAT) & psHu32(INTC_MASK)) {
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if ((cpuRegs.interrupt & (1 << 30)) == 0) {
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Console.Error("*PCSX2*: Error, missing INTC Interrupt");
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}
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}
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}
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__fi void _cpuTestMissingDMAC() {
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if (cpuRegs.CP0.n.Status.val & 0x800 &&
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(psHu16(0xe012) & psHu16(0xe010) ||
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psHu16(0xe010) & 0x8000)) {
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if ((cpuRegs.interrupt & (1 << 31)) == 0) {
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Console.Error("*PCSX2*: Error, missing DMAC Interrupt");
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}
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}
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}
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void cpuTestMissingHwInts() {
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if ((cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001) {
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_cpuTestMissingINTC();
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_cpuTestMissingDMAC();
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// _cpuTestTIMR();
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}
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}
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// sets a branch test to occur some time from an arbitrary starting point.
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__fi void cpuSetNextBranch( u32 startCycle, s32 delta )
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{
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@ -253,7 +226,7 @@ __fi void cpuSetNextBranchDelta( s32 delta )
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cpuSetNextBranch( cpuRegs.cycle, delta );
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}
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// tests the cpu cycle agaisnt the given start and delta values.
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// tests the cpu cycle against the given start and delta values.
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// Returns true if the delta time has passed.
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__fi int cpuTestCycle( u32 startCycle, s32 delta )
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{
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@ -361,8 +334,8 @@ static bool cpuIntsEnabled(int Interrupt)
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{
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bool IntType = !!(cpuRegs.CP0.n.Status.val & Interrupt); //Choose either INTC or DMAC, depending on what called it
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return cpuRegs.CP0.n.Status.b.EIE && cpuRegs.CP0.n.Status.b.IE &&
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!cpuRegs.CP0.n.Status.b.EXL && (cpuRegs.CP0.n.Status.b.ERL == 0) && IntType;
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return IntType && cpuRegs.CP0.n.Status.b.EIE && cpuRegs.CP0.n.Status.b.IE &&
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!cpuRegs.CP0.n.Status.b.EXL && (cpuRegs.CP0.n.Status.b.ERL == 0);
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}
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// if cpuRegs.cycle is greater than this cycle, should check cpuBranchTest for updates
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@ -375,10 +348,19 @@ __fi void _cpuBranchTest_Shared()
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ScopedBool etest(eeEventTestIsActive);
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g_nextBranchCycle = cpuRegs.cycle + eeWaitCycles;
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// ---- INTC / DMAC (CPU-level Exceptions) -----------------
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// Done first because exceptions raised during event tests need to be postponed a few
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// cycles (fixes Grandia II [PAL], which does a spin loop on a vsync and expects to
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// be able to read the value before the exception handler clears it).
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uint mask = intcInterrupt() | dmacInterrupt();
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if (cpuIntsEnabled(mask)) cpuException(mask, cpuRegs.branch);
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// ---- Counters -------------
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// Important: the vsync counter must be the first to be checked. It includes emulation
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// escape/suspend hooks, and it's really a good idea to suspend/resume emulation before
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// doing any actual meaninful branchtest logic.
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// doing any actual meaningful branchtest logic.
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if( cpuTestCycle( nextsCounter, nextCounter ) )
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{
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@ -391,10 +373,10 @@ __fi void _cpuBranchTest_Shared()
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_cpuTestTIMR();
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// ---- Interrupts -------------
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// Handles all interrupts except 30 and 31, which are handled later.
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// These are basically just DMAC-related events, which also piggy-back the same bits as
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// the PS2's own DMA channel IRQs and IRQ Masks.
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if( cpuRegs.interrupt & ~(3<<30) )
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_cpuTestInterrupts();
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_cpuTestInterrupts();
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// ---- IOP -------------
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// * It's important to run a psxBranchTest before calling ExecuteBlock. This
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@ -418,34 +400,7 @@ __fi void _cpuBranchTest_Shared()
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//if( EEsCycle < -450 )
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// Console.WriteLn( " IOP ahead by: %d cycles", -EEsCycle );
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// Experimental and Probably Unnecessary Logic -->
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// Check if the EE already has an exception pending, and if so we shouldn't
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// waste too much time updating the IOP. Theory being that the EE and IOP should
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// run closely in sync during raised exception events. But in practice it didn't
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// seem to make much of a difference.
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// Note: The IOP is very good about chaining blocks together so it tends to
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// run lots of cycles, even with only 32 (4 IOP) cycles specified here. That's
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// probably why it doesn't improve sync much.
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/*bool eeExceptPending = cpuIntsEnabled() &&
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//( cpuRegs.CP0.n.Status.b.EIE && cpuRegs.CP0.n.Status.b.IE && (cpuRegs.CP0.n.Status.b.ERL == 0) ) &&
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//( (cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001 ) &&
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( (cpuRegs.interrupt & (3<<30)) != 0 );
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if( eeExceptPending )
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{
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// ExecuteBlock returns a negative value, so subtract it from the cycle count
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// specified to get the total cycles processed! :D
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int cycleCount = std::min( EEsCycle, (s32)(eeWaitCycles>>4) );
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int cyclesRun = cycleCount - psxCpu->ExecuteBlock( cycleCount );
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EEsCycle -= cyclesRun;
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//Console.Warning( "IOP Exception-Pending Execution -- EEsCycle: %d", EEsCycle );
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}
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else*/
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{
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EEsCycle = psxCpu->ExecuteBlock( EEsCycle );
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}
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EEsCycle = psxCpu->ExecuteBlock( EEsCycle );
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iopBranchAction = false;
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}
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@ -479,32 +434,16 @@ __fi void _cpuBranchTest_Shared()
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// Apply vsync and other counter nextCycles
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cpuSetNextBranch( nextsCounter, nextCounter );
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// ---- INTC / DMAC Exceptions -----------------
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// Raise the INTC and DMAC interrupts here, which usually throw exceptions.
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// This should be done last since the IOP and the VU0 can raise several EE
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// exceptions.
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//if ((cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001)
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if( cpuIntsEnabled(0x400) ) TESTINT(30, intcInterrupt);
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if( cpuIntsEnabled(0x800) ) TESTINT(31, dmacInterrupt);
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}
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__ri void cpuTestINTCInts()
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{
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// Check the internal Event System -- if one's already scheduled then don't bother:
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if( cpuRegs.interrupt & (1 << 30) ) return;
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// Check the COP0's Status register for general interrupt disables, and the 0x400
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// bit (which is INTC master toggle).
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if( !cpuIntsEnabled(0x400) ) return;
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if( (psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0 ) return;
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cpuRegs.interrupt|= 1 << 30;
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cpuRegs.sCycle[30] = cpuRegs.cycle;
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cpuRegs.eCycle[30] = 4; //Needs to be 4 to account for bus delays/pipelines etc
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cpuSetNextBranchDelta( 4 );
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if(eeEventTestIsActive && (psxCycleEE > 0))
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{
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@ -515,9 +454,6 @@ __ri void cpuTestINTCInts()
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__fi void cpuTestDMACInts()
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{
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// Check the internal Event System -- if one's already scheduled then don't bother:
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if ( cpuRegs.interrupt & (1 << 31) ) return;
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// Check the COP0's Status register for general interrupt disables, and the 0x800
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// bit (which is the DMAC master toggle).
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if( !cpuIntsEnabled(0x800) ) return;
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@ -525,10 +461,6 @@ __fi void cpuTestDMACInts()
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if ( ( (psHu16(0xe012) & psHu16(0xe010)) == 0) &&
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( (psHu16(0xe010) & 0x8000) == 0) ) return;
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cpuRegs.interrupt|= 1 << 31;
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cpuRegs.sCycle[31] = cpuRegs.cycle;
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cpuRegs.eCycle[31] = 4; //Needs to be 4 to account for bus delays/pipelines etc
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cpuSetNextBranchDelta( 4 );
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if(eeEventTestIsActive && (psxCycleEE > 0))
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{
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@ -403,8 +403,8 @@ enum EE_EventType
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};
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extern void CPU_INT( EE_EventType n, s32 ecycle );
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extern void intcInterrupt();
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extern void dmacInterrupt();
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extern uint intcInterrupt();
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extern uint dmacInterrupt();
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extern void cpuInit();
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