Commit Graph

72 Commits

Author SHA1 Message Date
Arisotura 1dbe69c6be remove some debug crap 2020-12-10 18:09:11 +01:00
Arisotura 81964a0f89 make things function atleast somewhat
no pciture is being actually sent yet
2020-10-26 21:54:08 +01:00
Arisotura 8d42b1c7d7 messin' around 2020-09-08 20:19:37 +02:00
RSDuck f56aa60eb6 check IRQ first then Idle loop
apparently I put it this way for a reason
2020-07-28 00:44:58 +02:00
RSDuck 5903b11bda subtract cycles after checking IRQ and Halt
also switch back to adding to ARM::Cycles instead of subtracting from them
2020-07-27 23:14:39 +02:00
RSDuck 8a96dfce18 fix build with JIT disabled
fixes #675 and #674
2020-07-25 20:59:53 +02:00
RSDuck c5381d2911 reconcile DSi and JIT, fastmem for x64 and Windows 2020-06-30 23:50:41 +02:00
RSDuck e335a8ca76 first steps in bringing over the JIT refactor/fastmem 2020-06-16 12:11:19 +02:00
RSDuck 052ff73672 rewrite JIT memory emulation 2020-06-16 12:01:08 +02:00
RSDuck 6d217e1010 fix build with JIT disabled and set default JIT maxblock size to 32 2020-06-16 11:59:09 +02:00
RSDuck 1c07932b40 implement block linking + some refactoring
currently only supported for x64
2020-06-16 11:59:06 +02:00
RSDuck baed0ac0d5 remove debug leftovers 2020-06-16 11:57:50 +02:00
RSDuck ec965c6014 improve nop handling and proper behaviour for LDM^
fixes dslinux
2020-06-16 11:57:49 +02:00
RSDuck 1cfbbcbb2a make savestates 100% compatible again 2020-06-16 11:57:48 +02:00
RSDuck 441869a105 integrate changes from ARM64 backend and more
- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
2020-06-16 11:57:45 +02:00
RSDuck 40b88ab05a new block cache and much more...
- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
 and loads/stores from constant addresses
2020-06-16 11:56:36 +02:00
RSDuck 316378092a abandon pipelining on jit
fixes Golden Sun Dawn
this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state.
2020-06-16 11:55:24 +02:00
RSDuck 00cd9af033 fix uninitialised memory mapping 2020-06-16 11:54:47 +02:00
RSDuck 4deecc7d65 jit: decrease blockcache AddrMapping size for ARM9 2020-06-16 11:54:05 +02:00
RSDuck 86f2be7260 jit: add compile option 2020-06-16 11:54:03 +02:00
RSDuck d13d625f73 jit: make everything configurable 2020-06-16 11:53:21 +02:00
RSDuck f22521a43d jit: LDM/STM finally(!) working + MUL, MLA and CLZ 2020-06-16 11:53:10 +02:00
RSDuck 83bd863361 jit: branch instructions 2020-06-16 11:53:09 +02:00
RSDuck 10e386fe50 JIT: most mem instructions working
+ branching
2020-06-16 11:53:08 +02:00
RSDuck 2f6b46fd4f JIT: implemented most ALU instructions 2020-06-16 11:53:06 +02:00
RSDuck c692287eba JIT: base
all instructions are interpreted
2020-06-16 11:53:05 +02:00
Arisotura 43e045357f make it able to switch between DS and DSi modes 2020-06-01 20:36:30 +02:00
Arisotura 2327de2423 Merge commit '4b57416552ec2fa95216e2b044559f215723bf70' into melonDSi 2020-05-30 03:12:42 +02:00
Arisotura 5f99a68151 detect whether we are running the game 2020-02-24 18:31:44 +01:00
Arisotura 85a6a5bb38 * add support for a bunch of codes (all of them minus the loop shit, really)
* hook it betterer so it doesn't asplode
2020-02-14 23:34:26 +01:00
Arisotura 83f8e11bc1 update copyright years 2020-02-14 20:18:08 +01:00
Arisotura 81dde71eba add AES, fix a bunch of bugs
we're getting an error screen! wee
2019-06-19 14:24:49 +02:00
Arisotura 606a40e6b8 y'know, actually running the DMA units might yield better results. 2019-06-18 22:57:37 +02:00
Arisotura 78c41736c3 fix fucking ass-stupid bug with new-WRAM handling 2019-06-16 14:26:54 +02:00
Arisotura 4d3f346edc get it to do more interesting things 2019-06-15 18:30:12 +02:00
Arisotura 58e3ff61ac add I2C shito 2019-06-15 16:58:02 +02:00
Arisotura 09cfdc6e76 pft 2019-06-10 18:24:38 +02:00
Arisotura 434a3007e2 fasterer BG/OBJ VRAM reads 2019-06-09 16:06:01 +02:00
Arisotura 00a5576492 fasterer IRQ check. clean up code. 2019-06-08 22:16:51 +02:00
Arisotura 75f8cbf953 draft API for OpenGL shito in libui 2019-03-31 21:15:45 +02:00
Arisotura 4de4631c15 move platform specific config to platform specif ffile ayyyyyyyyyyygfghj;,gnxbf 2019-03-15 00:58:29 +01:00
Arisotura 93d51b0cbc start work on non-direct mode. reply to DHCP discover frame. 2019-02-23 13:41:51 +01:00
Arisotura b0efde8bf7 also, update copyright name 2019-01-22 15:58:29 +01:00
StapleButter 669247e8c8 redesign main emu loop to use timestamps instead of being a trainwreck
* cleaner code
* faster in some cases
* more accurate (on-demand compensation for timers and GPU)
* less prone to desyncs
* overall betterer
2019-01-05 05:28:58 +01:00
StapleButter 90f2c0834e add PoC ARM9 instruction cache logic. not actually in use, but it's there as a reference (and if we ever need it). 2019-01-04 21:47:06 +01:00
StapleButter 3101bd595f add missing shit to savestates. bump the version up. 2018-12-11 21:50:28 +01:00
StapleButter 4aafdee14d more sensible cache timings
(still a big fat hack)
2018-12-11 17:59:52 +01:00
StapleButter 91b2f64596 add back faster prefetch for ARM9 2018-12-11 16:41:18 +01:00
StapleButter 3dd8c7b152 finish the work on the main loop. finally fix all cases of desync I could find. also add #ifdef'd debug code to check for desyncs. 2018-12-11 15:56:34 +01:00
StapleButter 78d384a754 temp commit
almost done killing ARM9/ARM7 desync, f
2018-12-11 03:08:46 +01:00