fasterer IRQ check. clean up code.
This commit is contained in:
Arisotura
parent
8fc30d69c5
commit
00a5576492
31
src/ARM.cpp
31
src/ARM.cpp
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@ -83,6 +83,8 @@ void ARM::Reset()
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Cycles = 0;
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Halted = 0;
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IRQ = 0;
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for (int i = 0; i < 16; i++)
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R[i] = 0;
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@ -173,23 +175,6 @@ void ARMv5::JumpTo(u32 addr, bool restorecpsr)
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// aging cart debug crap
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//if (addr == 0x0201764C) printf("capture test %d: R1=%08X\n", R[6], R[1]);
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//if (addr == 0x020175D8) printf("capture test %d: res=%08X\n", R[6], R[0]);
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// R0=DMA# R1=src R2=size
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//if (addr==0x02019A88) printf("[%08X] [%03d] GX FIFO CMD %08X\n", R[15], NDS::ARM9Read16(0x04000006), R[0]);
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//if (addr==0x02022A5C) printf("[%08X] [%03d|%04X] RENDE SHITO %08X\n", R[15], NDS::ARM9Read16(0x04000006), NDS::ARM9Read16(0x04000304), R[0]);
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/*if (addr==0x0204BE29) printf("%08X -> recvfrom\n", R[15]);
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if (R[15]==0x0204BE5E) printf("recvfrom() ret:%d errno:%d %08X\n", R[0], NDS::ARM9Read32(0x217F398), addr);
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if (R[15]==0x0205038A) printf("sgrecvfrom() ret:%d errno:%d %08X\n", R[0], NDS::ARM9Read32(0x217F398), addr);
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if (addr==0x02050379 || addr==0x0205036D) printf("morp %08X->%08X, %d\n", R[15], addr, R[7]);*/
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/*if (addr==0x020B5F14) printf("VRAM UNMAP %02X %08X\n", R[0], R[15]);
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if (addr==0x020B5FAC) printf("VRAM MAP %2X %08X\n", R[0], R[15]);
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if (addr==0x0209F860) printf("VRAM BLORP %02X %08X\n", R[0], R[15]);
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if (addr==0x02005A34) printf("VAZAVAZORP %08X. VCOUNT=%d\n", R[15], NDS::ARM9Read16(0x04000006));
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if (addr==0x0209FBEC) printf("COUILLON. %08X %08X\n", R[0], R[1]);
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if (addr==0x02004AA8) printf("ANEBATE 1 %d\n", NDS::ARM9Read16(0x04000006));
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if (addr==0x020058C8) printf("ANEBATE 2 %d\n", NDS::ARM9Read16(0x04000006));
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if (addr==0x02005398) printf("ANEBATE 3 %d %d\n", NDS::ARM9Read16(0x04000006), (u32)(NDS::ARM9Timestamp-vbltime));
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if (addr==0x02005A5C) printf("PLAFORP %d\n", NDS::ARM9Read16(0x04000006));
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if (addr==0x209FBDC) printf("ROLOLORP\n");*/
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u32 oldregion = R[15] >> 24;
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u32 newregion = addr >> 24;
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@ -518,8 +503,6 @@ void ARMv5::Execute()
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}
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else
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AddCycles_C();
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//if (R[15]>=0x02005A5C && R[15]<=0x02005A84) printf("NORP %08X %d\n", R[15]-8, NDS::ARM9Read16(0x04000006));
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}
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// TODO optimize this shit!!!
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@ -531,11 +514,12 @@ void ARMv5::Execute()
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}
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break;
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}
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if (NDS::IF[0] & NDS::IE[0])
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/*if (NDS::IF[0] & NDS::IE[0])
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{
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if (NDS::IME[0] & 0x1)
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TriggerIRQ();
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}
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}*/
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if (IRQ) TriggerIRQ();
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NDS::ARM9Timestamp += Cycles;
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Cycles = 0;
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@ -607,11 +591,12 @@ void ARMv4::Execute()
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}
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break;
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}
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if (NDS::IF[1] & NDS::IE[1])
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/*if (NDS::IF[1] & NDS::IE[1])
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{
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if (NDS::IME[1] & 0x1)
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TriggerIRQ();
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}
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}*/
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if (IRQ) TriggerIRQ();
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NDS::ARM7Timestamp += Cycles;
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Cycles = 0;
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12
src/ARM.h
12
src/ARM.h
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@ -51,16 +51,6 @@ public:
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Halted = halt;
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}
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// TODO: is this actually used??
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void CheckIRQ()
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{
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if (!(NDS::IME[Num] & 0x1)) return;
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if (NDS::IF[Num] & NDS::IE[Num])
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{
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TriggerIRQ();
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}
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}
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virtual void Execute() = 0;
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bool CheckCondition(u32 code)
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@ -119,6 +109,8 @@ public:
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s32 Cycles;
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u32 Halted;
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u32 IRQ; // nonzero to trigger IRQ
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u32 CodeRegion;
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s32 CodeCycles;
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44
src/NDS.cpp
44
src/NDS.cpp
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@ -1044,14 +1044,30 @@ void SetGBASlotTimings()
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}
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void UpdateIRQ(u32 cpu)
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{
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ARM* arm = cpu ? (ARM*)ARM7 : (ARM*)ARM9;
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if (IME[cpu] & 0x1)
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{
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arm->IRQ = IE[cpu] & IF[cpu];
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}
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else
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{
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arm->IRQ = 0;
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}
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}
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void SetIRQ(u32 cpu, u32 irq)
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{
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IF[cpu] |= (1 << irq);
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UpdateIRQ(cpu);
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}
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void ClearIRQ(u32 cpu, u32 irq)
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{
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IF[cpu] &= ~(1 << irq);
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UpdateIRQ(cpu);
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}
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bool HaltInterrupted(u32 cpu)
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@ -2599,7 +2615,7 @@ void ARM9IOWrite8(u32 addr, u8 val)
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case 0x040001AE: NDSCart::ROMCommand[6] = val; return;
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case 0x040001AF: NDSCart::ROMCommand[7] = val; return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000208: IME[0] = val & 0x1; UpdateIRQ(0); return;
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case 0x04000240: GPU::MapVRAM_AB(0, val); return;
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case 0x04000241: GPU::MapVRAM_AB(1, val); return;
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@ -2739,9 +2755,9 @@ void ARM9IOWrite16(u32 addr, u16 val)
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SetGBASlotTimings();
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return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000210: IE[0] = (IE[0] & 0xFFFF0000) | val; return;
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case 0x04000212: IE[0] = (IE[0] & 0x0000FFFF) | (val << 16); return;
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case 0x04000208: IME[0] = val & 0x1; UpdateIRQ(0); return;
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case 0x04000210: IE[0] = (IE[0] & 0xFFFF0000) | val; UpdateIRQ(0); return;
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case 0x04000212: IE[0] = (IE[0] & 0x0000FFFF) | (val << 16); UpdateIRQ(0); return;
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// TODO: what happens when writing to IF this way??
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case 0x04000240:
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@ -2894,9 +2910,9 @@ void ARM9IOWrite32(u32 addr, u32 val)
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case 0x040001B0: *(u32*)&ROMSeed0[0] = val; return;
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case 0x040001B4: *(u32*)&ROMSeed1[0] = val; return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000210: IE[0] = val; return;
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case 0x04000214: IF[0] &= ~val; GPU3D::CheckFIFOIRQ(); return;
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case 0x04000208: IME[0] = val & 0x1; UpdateIRQ(0); return;
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case 0x04000210: IE[0] = val; UpdateIRQ(0); return;
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case 0x04000214: IF[0] &= ~val; GPU3D::CheckFIFOIRQ(); UpdateIRQ(0); return;
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case 0x04000240:
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GPU::MapVRAM_AB(0, val & 0xFF);
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@ -3211,7 +3227,7 @@ void ARM7IOWrite8(u32 addr, u8 val)
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SPI::WriteData(val);
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return;
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case 0x04000208: IME[1] = val & 0x1; return;
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case 0x04000208: IME[1] = val & 0x1; UpdateIRQ(1); return;
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case 0x04000300:
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if (ARM7->R[15] >= 0x4000)
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@ -3333,9 +3349,9 @@ void ARM7IOWrite16(u32 addr, u16 val)
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SetWifiWaitCnt(val);
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return;
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case 0x04000208: IME[1] = val & 0x1; return;
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case 0x04000210: IE[1] = (IE[1] & 0xFFFF0000) | val; return;
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case 0x04000212: IE[1] = (IE[1] & 0x0000FFFF) | (val << 16); return;
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case 0x04000208: IME[1] = val & 0x1; UpdateIRQ(1); return;
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case 0x04000210: IE[1] = (IE[1] & 0xFFFF0000) | val; UpdateIRQ(1); return;
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case 0x04000212: IE[1] = (IE[1] & 0x0000FFFF) | (val << 16); UpdateIRQ(1); return;
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// TODO: what happens when writing to IF this way??
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case 0x04000300:
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@ -3445,9 +3461,9 @@ void ARM7IOWrite32(u32 addr, u32 val)
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case 0x040001B0: *(u32*)&ROMSeed0[8] = val; return;
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case 0x040001B4: *(u32*)&ROMSeed1[8] = val; return;
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case 0x04000208: IME[1] = val & 0x1; return;
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case 0x04000210: IE[1] = val; return;
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case 0x04000214: IF[1] &= ~val; return;
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case 0x04000208: IME[1] = val & 0x1; UpdateIRQ(1); return;
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case 0x04000210: IE[1] = val; UpdateIRQ(1); return;
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case 0x04000214: IF[1] &= ~val; UpdateIRQ(1); return;
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case 0x04000308:
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if (ARM7BIOSProt == 0)
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