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rewrite JIT memory emulation

This commit is contained in:
RSDuck 2020-05-09 00:45:05 +02:00
parent b902cd1b8e
commit 052ff73672
14 changed files with 1494 additions and 844 deletions
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10
src/ARM.cpp
View File

@ -622,7 +622,8 @@ void ARMv5::ExecuteJIT()
while (NDS::ARM9Timestamp < NDS::ARM9Target)
{
u32 instrAddr = R[15] - ((CPSR&0x20)?2:4);
if (!ARMJIT::IsMapped<0>(instrAddr))
u32 translatedAddr = ARMJIT::TranslateAddr9(instrAddr);
if (!translatedAddr)
{
NDS::ARM9Timestamp = NDS::ARM9Target;
printf("ARMv5 PC in non executable region %08X\n", R[15]);
@ -632,7 +633,7 @@ void ARMv5::ExecuteJIT()
// hack so Cycles <= 0 becomes Cycles < 0
Cycles = NDS::ARM9Target - NDS::ARM9Timestamp - 1;
ARMJIT::JitBlockEntry block = ARMJIT::LookUpBlockEntry(ARMJIT::TranslateAddr<0>(instrAddr));
ARMJIT::JitBlockEntry block = ARMJIT::LookUpBlockEntry<0>(translatedAddr);
if (block)
ARM_Dispatch(this, block);
else
@ -765,7 +766,8 @@ void ARMv4::ExecuteJIT()
while (NDS::ARM7Timestamp < NDS::ARM7Target)
{
u32 instrAddr = R[15] - ((CPSR&0x20)?2:4);
if (!ARMJIT::IsMapped<1>(instrAddr))
u32 translatedAddr = ARMJIT::TranslateAddr7(instrAddr);
if (!translatedAddr)
{
NDS::ARM7Timestamp = NDS::ARM7Target;
printf("ARMv4 PC in non executable region %08X\n", R[15]);
@ -774,7 +776,7 @@ void ARMv4::ExecuteJIT()
Cycles = NDS::ARM7Target - NDS::ARM7Timestamp - 1;
ARMJIT::JitBlockEntry block = ARMJIT::LookUpBlockEntry(ARMJIT::TranslateAddr<1>(instrAddr));
ARMJIT::JitBlockEntry block = ARMJIT::LookUpBlockEntry<1>(translatedAddr);
if (block)
ARM_Dispatch(this, block);
else

24
src/ARM.h
View File

@ -320,7 +320,7 @@ public:
void DataRead8(u32 addr, u32* val)
{
*val = BusRead8(addr);
DataRegion = addr >> 20;
DataRegion = addr;
DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
}
@ -329,7 +329,7 @@ public:
addr &= ~1;
*val = BusRead16(addr);
DataRegion = addr >> 20;
DataRegion = addr;
DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
}
@ -338,7 +338,7 @@ public:
addr &= ~3;
*val = BusRead32(addr);
DataRegion = addr >> 20;
DataRegion = addr;
DataCycles = NDS::ARM7MemTimings[addr >> 15][2];
}
@ -353,7 +353,7 @@ public:
void DataWrite8(u32 addr, u8 val)
{
BusWrite8(addr, val);
DataRegion = addr >> 20;
DataRegion = addr;
DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
}
@ -362,7 +362,7 @@ public:
addr &= ~1;
BusWrite16(addr, val);
DataRegion = addr >> 20;
DataRegion = addr;
DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
}
@ -371,7 +371,7 @@ public:
addr &= ~3;
BusWrite32(addr, val);
DataRegion = addr >> 20;
DataRegion = addr;
DataCycles = NDS::ARM7MemTimings[addr >> 15][2];
}
@ -402,7 +402,7 @@ public:
s32 numC = NDS::ARM7MemTimings[CodeCycles][(CPSR&0x20)?0:2];
s32 numD = DataCycles;
if ((DataRegion >> 4) == 0x02) // mainRAM
if ((DataRegion >> 24) == 0x02) // mainRAM
{
if (CodeRegion == 0x02)
Cycles -= numC + numD;
@ -429,7 +429,7 @@ public:
s32 numC = NDS::ARM7MemTimings[CodeCycles][(CPSR&0x20)?0:2];
s32 numD = DataCycles;
if ((DataRegion >> 4) == 0x02)
if ((DataRegion >> 24) == 0x02)
{
if (CodeRegion == 0x02)
Cycles -= numC + numD;
@ -455,4 +455,12 @@ void T_UNK(ARM* cpu);
}
namespace NDS
{
extern ARMv5* ARM9;
extern ARMv4* ARM7;
}
#endif // ARM_H

907
src/ARMJIT.cpp
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File diff suppressed because it is too large Load Diff

65
src/ARMJIT.h
View File

@ -28,45 +28,60 @@ extern const u32 ExeMemRegionSizes[];
typedef u32 (*JitBlockEntry)();
extern u32 AddrTranslate9[0x2000];
extern u32 AddrTranslate7[0x4000];
const u32 ExeMemSpaceSize = 0x518000; // I hate you C++, sometimes I really hate you...
template <u32 num>
inline bool IsMapped(u32 addr)
{
if (num == 0)
return AddrTranslate9[(addr & 0xFFFFFFF) >> 15] >= ExeMemRegionSizes[exeMem_Unmapped];
else
return AddrTranslate7[(addr & 0xFFFFFFF) >> 14] >= ExeMemRegionSizes[exeMem_Unmapped];
}
template <u32 num>
inline u32 TranslateAddr(u32 addr)
{
if (num == 0)
return AddrTranslate9[(addr & 0xFFFFFFF) >> 15] + (addr & 0x7FFF);
else
return AddrTranslate7[(addr & 0xFFFFFFF) >> 14] + (addr & 0x3FFF);
}
u32 TranslateAddr9(u32 addr);
u32 TranslateAddr7(u32 addr);
template <u32 Num>
JitBlockEntry LookUpBlockEntry(u32 addr);
void Init();
void DeInit();
void InvalidateByAddr(u32 pseudoPhysical, bool mayRestore = true);
void InvalidateAll();
void Reset();
void InvalidateITCM(u32 addr);
void InvalidateByAddr7(u32 addr);
void InvalidateByAddr(u32 pseudoPhysical);
void InvalidateRegionIfNecessary(u32 addr);
inline void InvalidateMainRAMIfNecessary(u32 addr)
{
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_MainRAM] + (addr & (MAIN_RAM_SIZE - 1)));
}
inline void InvalidateITCMIfNecessary(u32 addr)
{
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_ITCM] + (addr & 0x7FFF));
}
inline void InvalidateLCDCIfNecessary(u32 addr)
{
if (addr < 0x68A3FFF)
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_LCDC] + (addr - 0x6800000));
}
inline void InvalidateSWRAM7IfNecessary(u32 addr)
{
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_SWRAM] + (NDS::SWRAM_ARM7 - NDS::SharedWRAM) + (addr & NDS::SWRAM_ARM7Mask));
}
inline void InvalidateSWRAM9IfNecessary(u32 addr)
{
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_SWRAM] + (NDS::SWRAM_ARM9 - NDS::SharedWRAM) + (addr & NDS::SWRAM_ARM9Mask));
}
inline void InvalidateARM7WRAMIfNecessary(u32 addr)
{
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_ARM7_WRAM] + (addr & 0xFFFF));
}
inline void InvalidateARM7WVRAMIfNecessary(u32 addr)
{
InvalidateRegionIfNecessary(ExeMemRegionOffsets[exeMem_ARM7_WVRAM] + (addr & 0x1FFFF));
}
void CompileBlock(ARM* cpu);
void ResetBlockCache();
void UpdateMemoryStatus9(u32 start, u32 end);
void UpdateMemoryStatus7(u32 start, u32 end);
}
extern "C" void ARM_Dispatch(ARM* cpu, ARMJIT::JitBlockEntry entry);

4
src/ARMJIT_A64/ARMJIT_Compiler.cpp
View File

@ -650,7 +650,7 @@ void Compiler::Comp_AddCycles_CDI()
s32 numC = NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
s32 numD = CurInstr.DataCycles;
if ((CurInstr.DataRegion >> 4) == 0x02) // mainRAM
if ((CurInstr.DataRegion >> 24) == 0x02) // mainRAM
{
if (CodeRegion == 0x02)
cycles = numC + numD;
@ -695,7 +695,7 @@ void Compiler::Comp_AddCycles_CD()
s32 numC = NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
s32 numD = CurInstr.DataCycles;
if ((CurInstr.DataRegion >> 4) == 0x02)
if ((CurInstr.DataRegion >> 24) == 0x02)
{
if (CodeRegion == 0x02)
cycles += numC + numD;

68
src/ARMJIT_Internal.h
View File

@ -152,30 +152,34 @@ struct __attribute__((packed)) TinyVector
class JitBlock
{
public:
JitBlock(u32 numInstrs, u32 numAddresses)
JitBlock(u32 num, u32 literalHash, u32 numAddresses, u32 numLiterals)
{
NumInstrs = numInstrs;
Num = num;
NumAddresses = numAddresses;
Data.SetLength(numInstrs + numAddresses);
NumLiterals = numLiterals;
Data.SetLength(numAddresses * 2 + numLiterals);
}
u32 StartAddr;
u32 PseudoPhysicalAddr;
u32 NumInstrs;
u32 NumAddresses;
u32 InstrHash, LiteralHash;
u8 Num;
u16 NumAddresses;
u16 NumLiterals;
JitBlockEntry EntryPoint;
u32* Instrs()
{ return &Data[0]; }
u32* AddressRanges()
{ return &Data[NumInstrs]; }
{ return &Data[0]; }
u32* AddressMasks()
{ return &Data[NumAddresses]; }
u32* Literals()
{ return &Data[NumAddresses * 2]; }
u32* Links()
{ return &Data[NumInstrs + NumAddresses]; }
{ return &Data[NumAddresses * 2 + NumLiterals]; }
u32 NumLinks()
{ return Data.Length - NumInstrs - NumAddresses; }
{ return Data.Length - NumAddresses * 2 - NumLiterals; }
void AddLink(u32 link)
{
@ -184,7 +188,7 @@ public:
void ResetLinks()
{
Data.SetLength(NumInstrs + NumAddresses);
Data.SetLength(NumAddresses * 2 + NumLiterals);
}
private:
@ -200,8 +204,7 @@ private:
struct __attribute__((packed)) AddressRange
{
TinyVector<JitBlock*> Blocks;
u16 InvalidLiterals;
u16 TimesInvalidated;
u32 Code;
};
extern AddressRange CodeRanges[ExeMemSpaceSize / 512];
@ -210,14 +213,45 @@ typedef void (*InterpreterFunc)(ARM* cpu);
extern InterpreterFunc InterpretARM[];
extern InterpreterFunc InterpretTHUMB[];
extern u8 MemRegion9[0x80000];
extern u8 MemRegion7[0x80000];
extern u8 MemoryStatus9[0x800000];
extern u8 MemoryStatus7[0x800000];
extern TinyVector<u32> InvalidLiterals;
void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size);
template <u32 Num>
void LinkBlock(ARM* cpu, u32 codeOffset);
enum
{
memregion_Other = 0,
memregion_ITCM,
memregion_DTCM,
memregion_BIOS9,
memregion_MainRAM,
memregion_SWRAM9,
memregion_SWRAM7,
memregion_IO9,
memregion_VRAM,
memregion_BIOS7,
memregion_WRAM7,
memregion_IO7,
memregion_Wifi,
memregion_VWRAM,
};
int ClassifyAddress9(u32 addr);
int ClassifyAddress7(u32 addr);
template <typename T> T SlowRead9(ARMv5* cpu, u32 addr);
template <typename T> void SlowWrite9(ARMv5* cpu, u32 addr, T val);
template <typename T> T SlowRead7(u32 addr);
template <typename T> void SlowWrite7(u32 addr, T val);
template <bool PreInc, bool Write> void SlowBlockTransfer9(u32 addr, u64* data, u32 num, ARMv5* cpu);
template <bool PreInc, bool Write> void SlowBlockTransfer7(u32 addr, u64* data, u32 num);
}
#endif

18
src/ARMJIT_RegisterCache.h
View File

@ -95,20 +95,6 @@ public:
LiteralsLoaded = 0;
}
BitSet32 GetPushRegs()
{
BitSet16 used;
for (int i = 0; i < InstrsCount; i++)
used |= BitSet16(Instrs[i].Info.SrcRegs | Instrs[i].Info.DstRegs);
BitSet32 res;
u32 registersMax = std::min((int)used.Count(), NativeRegsAvailable);
for (int i = 0; i < registersMax; i++)
res |= BitSet32(1 << (int)NativeRegAllocOrder[i]);
return res;
}
void Prepare(bool thumb, int i)
{
FetchedInstr instr = Instrs[i];
@ -139,7 +125,6 @@ public:
UnloadRegister(reg);
u16 necessaryRegs = ((instr.Info.SrcRegs & PCAllocatableAsSrc) | instr.Info.DstRegs) & ~instr.Info.NotStrictlyNeeded;
u16 writeRegs = instr.Info.DstRegs & ~instr.Info.NotStrictlyNeeded;
BitSet16 needToBeLoaded(necessaryRegs & ~LoadedRegs);
if (needToBeLoaded != BitSet16(0))
{
@ -182,13 +167,12 @@ public:
if (left-- == 0)
break;
writeRegs |= (1 << reg) & instr.Info.DstRegs;
LoadRegister(reg, !(thumb || instr.Cond() >= 0xE) || (1 << reg) & instr.Info.SrcRegs);
}
}
}
DirtyRegs |= writeRegs & ~(1 << 15);
DirtyRegs |= (LoadedRegs & instr.Info.DstRegs) & ~(1 << 15);
}
static const Reg NativeRegAllocOrder[];

43
src/ARMJIT_x64/ARMJIT_Compiler.cpp
View File

@ -195,26 +195,6 @@ Compiler::Compiler()
Reset();
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 2; j++)
MemoryFuncs9[i][j] = Gen_MemoryRoutine9(j, 8 << i);
}
MemoryFuncs7[0][0] = (void*)NDS::ARM7Read8;
MemoryFuncs7[0][1] = (void*)NDS::ARM7Write8;
MemoryFuncs7[1][0] = (void*)NDS::ARM7Read16;
MemoryFuncs7[1][1] = (void*)NDS::ARM7Write16;
MemoryFuncs7[2][0] = (void*)NDS::ARM7Read32;
MemoryFuncs7[2][1] = (void*)NDS::ARM7Write32;
for (int i = 0; i < 2; i++)
for (int j = 0; j < 2; j++)
{
MemoryFuncsSeq9[i][j] = Gen_MemoryRoutineSeq9(i, j);
MemoryFuncsSeq7[i][j][0] = Gen_MemoryRoutineSeq7(i, j, false);
MemoryFuncsSeq7[i][j][1] = Gen_MemoryRoutineSeq7(i, j, true);
}
{
// RSCRATCH mode
// RSCRATCH2 reg number
@ -317,6 +297,12 @@ Compiler::Compiler()
// move the region forward to prevent overwriting the generated functions
CodeMemSize -= GetWritableCodePtr() - ResetStart;
ResetStart = GetWritableCodePtr();
NearStart = ResetStart;
FarStart = ResetStart + 1024*1024*24;
NearSize = FarStart - ResetStart;
FarSize = (ResetStart + CodeMemSize) - FarStart;
}
void Compiler::LoadCPSR()
@ -504,6 +490,9 @@ void Compiler::Reset()
{
memset(ResetStart, 0xcc, CodeMemSize);
SetCodePtr(ResetStart);
NearCode = NearStart;
FarCode = FarStart;
}
void Compiler::Comp_SpecialBranchBehaviour(bool taken)
@ -544,8 +533,16 @@ void Compiler::Comp_SpecialBranchBehaviour(bool taken)
JitBlockEntry Compiler::CompileBlock(u32 translatedAddr, ARM* cpu, bool thumb, FetchedInstr instrs[], int instrsCount)
{
if (CodeMemSize - (GetWritableCodePtr() - ResetStart) < 1024 * 32) // guess...
if (NearSize - (NearCode - NearStart) < 1024 * 32) // guess...
{
printf("near reset\n");
ResetBlockCache();
}
if (FarSize - (FarCode - FarStart) < 1024 * 32) // guess...
{
printf("far reset\n");
ResetBlockCache();
}
ConstantCycles = 0;
Thumb = thumb;
@ -762,12 +759,14 @@ void Compiler::Comp_AddCycles_CDI()
Comp_AddCycles_CD();
else
{
IrregularCycles = true;
s32 cycles;
s32 numC = NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
s32 numD = CurInstr.DataCycles;
if ((CurInstr.DataRegion >> 4) == 0x02) // mainRAM
if ((CurInstr.DataRegion >> 24) == 0x02) // mainRAM
{
if (CodeRegion == 0x02)
cycles = numC + numD;

34
src/ARMJIT_x64/ARMJIT_Compiler.h
View File

@ -140,7 +140,7 @@ public:
};
void Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int size, int flags);
s32 Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode);
void Comp_MemLoadLiteral(int size, int rd, u32 addr);
bool Comp_MemLoadLiteral(int size, int rd, u32 addr);
void Comp_ArithTriOp(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
@ -154,12 +154,6 @@ public:
void Comp_SpecialBranchBehaviour(bool taken);
void* Gen_MemoryRoutine9(bool store, int size);
void* Gen_MemoryRoutineSeq9(bool store, bool preinc);
void* Gen_MemoryRoutineSeq7(bool store, bool preinc, bool codeMainRAM);
void* Gen_ChangeCPSRRoutine();
Gen::OpArg Comp_RegShiftImm(int op, int amount, Gen::OpArg rm, bool S, bool& carryUsed);
Gen::OpArg Comp_RegShiftReg(int op, Gen::OpArg rs, Gen::OpArg rm, bool S, bool& carryUsed);
@ -193,6 +187,26 @@ public:
return (u8*)entry - ResetStart;
}
void SwitchToNearCode()
{
FarCode = GetWritableCodePtr();
SetCodePtr(NearCode);
}
void SwitchToFarCode()
{
NearCode = GetWritableCodePtr();
SetCodePtr(FarCode);
}
u8* FarCode;
u8* NearCode;
u32 FarSize;
u32 NearSize;
u8* NearStart;
u8* FarStart;
u8* ResetStart;
u32 CodeMemSize;
@ -201,12 +215,6 @@ public:
void* BranchStub[2];
void* MemoryFuncs9[3][2];
void* MemoryFuncs7[3][2];
void* MemoryFuncsSeq9[2][2];
void* MemoryFuncsSeq7[2][2][2];
void* ReadBanked;
void* WriteBanked;

991
src/ARMJIT_x64/ARMJIT_LoadStore.cpp
View File

File diff suppressed because it is too large Load Diff

16
src/ARM_InstrInfo.cpp
View File

@ -373,16 +373,16 @@ Info Decode(bool thumb, u32 num, u32 instr)
if (res.Kind == tk_LDMIA || res.Kind == tk_POP)
{
u32 set = (instr & 0xFF) & ~(res.DstRegs|res.SrcRegs);
res.NotStrictlyNeeded |= set;
u32 set = (instr & 0xFF);
res.NotStrictlyNeeded |= set & ~(res.DstRegs|res.SrcRegs);
res.DstRegs |= set;
}
if (res.Kind == tk_STMIA || res.Kind == tk_PUSH)
{
u32 set = (instr & 0xFF) & ~(res.DstRegs|res.SrcRegs);
u32 set = (instr & 0xFF);
if (res.Kind == tk_PUSH && instr & (1 << 8))
set |= (1 << 14);
res.NotStrictlyNeeded |= set;
res.NotStrictlyNeeded |= set & ~(res.DstRegs|res.SrcRegs);
res.SrcRegs |= set;
}
@ -495,15 +495,15 @@ Info Decode(bool thumb, u32 num, u32 instr)
if (res.Kind == ak_LDM)
{
u16 set = (instr & 0xFFFF) & ~(res.SrcRegs|res.DstRegs|(1<<15));
u16 set = (instr & 0xFFFF);
res.NotStrictlyNeeded |= set & ~(res.SrcRegs|res.DstRegs|(1<<15));
res.DstRegs |= set;
res.NotStrictlyNeeded |= set;
}
if (res.Kind == ak_STM)
{
u16 set = (instr & 0xFFFF) & ~(res.SrcRegs|res.DstRegs|(1<<15));
u16 set = (instr & 0xFFFF);
res.NotStrictlyNeeded |= set & ~(res.SrcRegs|res.DstRegs|(1<<15));
res.SrcRegs |= set;
res.NotStrictlyNeeded |= set;
}
if ((instr >> 28) < 0xE)

44
src/CP15.cpp
View File

@ -98,6 +98,10 @@ void ARMv5::CP15DoSavestate(Savestate* file)
void ARMv5::UpdateDTCMSetting()
{
#ifdef JIT_ENABLED
u32 oldDTCMBase = DTCMBase;
u32 oldDTCMSize = DTCMSize;
#endif
if (CP15Control & (1<<16))
{
DTCMBase = DTCMSetting & 0xFFFFF000;
@ -110,10 +114,20 @@ void ARMv5::UpdateDTCMSetting()
DTCMSize = 0;
//printf("DTCM disabled\n");
}
#ifdef JIT_ENABLED
if (oldDTCMBase != DTCMBase || oldDTCMSize != DTCMSize)
{
ARMJIT::UpdateMemoryStatus9(oldDTCMBase, oldDTCMBase + oldDTCMSize);
ARMJIT::UpdateMemoryStatus9(DTCMBase, DTCMBase + DTCMSize);
}
#endif
}
void ARMv5::UpdateITCMSetting()
{
#ifdef JIT_ENABLED
u32 oldITCMSize = ITCMSize;
#endif
if (CP15Control & (1<<18))
{
ITCMSize = 0x200 << ((ITCMSetting >> 1) & 0x1F);
@ -124,6 +138,10 @@ void ARMv5::UpdateITCMSetting()
ITCMSize = 0;
//printf("ITCM disabled\n");
}
#ifdef JIT_ENABLED
if (oldITCMSize != ITCMSize)
ARMJIT::UpdateMemoryStatus9(0, std::max(oldITCMSize, ITCMSize));
#endif
}
@ -562,15 +580,9 @@ void ARMv5::CP15Write(u32 id, u32 val)
case 0x750:
#ifdef JIT_ENABLED
ARMJIT::InvalidateAll();
#endif
ICacheInvalidateAll();
return;
case 0x751:
#ifdef JIT_ENABLED
ARMJIT::InvalidateByAddr(ARMJIT::TranslateAddr<0>(val));
#endif
ICacheInvalidateByAddr(val);
return;
case 0x752:
@ -733,7 +745,7 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
void ARMv5::DataRead8(u32 addr, u32* val)
{
DataRegion = addr >> 12;
DataRegion = addr;
if (addr < ITCMSize)
{
@ -754,7 +766,7 @@ void ARMv5::DataRead8(u32 addr, u32* val)
void ARMv5::DataRead16(u32 addr, u32* val)
{
DataRegion = addr >> 12;
DataRegion = addr;
addr &= ~1;
@ -777,7 +789,7 @@ void ARMv5::DataRead16(u32 addr, u32* val)
void ARMv5::DataRead32(u32 addr, u32* val)
{
DataRegion = addr >> 12;
DataRegion = addr;
addr &= ~3;
@ -821,14 +833,14 @@ void ARMv5::DataRead32S(u32 addr, u32* val)
void ARMv5::DataWrite8(u32 addr, u8 val)
{
DataRegion = addr >> 12;
DataRegion = addr;
if (addr < ITCMSize)
{
DataCycles = 1;
*(u8*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateITCM(addr & 0x7FFF);
ARMJIT::InvalidateITCMIfNecessary(addr);
#endif
return;
}
@ -845,7 +857,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
void ARMv5::DataWrite16(u32 addr, u16 val)
{
DataRegion = addr >> 12;
DataRegion = addr;
addr &= ~1;
@ -854,7 +866,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
DataCycles = 1;
*(u16*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateITCM(addr & 0x7FFF);
ARMJIT::InvalidateITCMIfNecessary(addr);
#endif
return;
}
@ -871,7 +883,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
void ARMv5::DataWrite32(u32 addr, u32 val)
{
DataRegion = addr >> 12;
DataRegion = addr;
addr &= ~3;
@ -880,7 +892,7 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
DataCycles = 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateITCM(addr & 0x7FFF);
ARMJIT::InvalidateITCMIfNecessary(addr);
#endif
return;
}
@ -904,7 +916,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
DataCycles += 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateITCM(addr & 0x7FFF);
ARMJIT::InvalidateITCMIfNecessary(addr);
#endif
return;
}

105
src/NDS.cpp
View File

@ -574,10 +574,6 @@ void Reset()
KeyCnt = 0;
RCnt = 0;
#ifdef JIT_ENABLED
ARMJIT::ResetBlockCache();
#endif
NDSCart::Reset();
GBACart::Reset();
GPU::Reset();
@ -593,6 +589,10 @@ void Reset()
}
AREngine::Reset();
#ifdef JIT_ENABLED
ARMJIT::Reset();
#endif
}
void Stop()
@ -1127,6 +1127,9 @@ void Halt()
void MapSharedWRAM(u8 val)
{
if (val == WRAMCnt)
return;
WRAMCnt = val;
switch (WRAMCnt & 0x3)
@ -1159,6 +1162,11 @@ void MapSharedWRAM(u8 val)
SWRAM_ARM7Mask = 0x7FFF;
break;
}
#ifdef JIT_ENABLED
ARMJIT::UpdateMemoryStatus9(0x3000000, 0x3000000 + 0x1000000);
ARMJIT::UpdateMemoryStatus7(0x3000000, 0x3000000 + 0x1000000);
#endif
}
@ -2020,11 +2028,17 @@ void ARM9Write8(u32 addr, u8 val)
{
case 0x02000000:
*(u8*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateMainRAMIfNecessary(addr);
#endif
return;
case 0x03000000:
if (SWRAM_ARM9)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateSWRAM9IfNecessary(addr);
#endif
*(u8*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask] = val;
}
return;
@ -2070,11 +2084,17 @@ void ARM9Write16(u32 addr, u16 val)
{
case 0x02000000:
*(u16*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateMainRAMIfNecessary(addr);
#endif
return;
case 0x03000000:
if (SWRAM_ARM9)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateSWRAM9IfNecessary(addr);
#endif
*(u16*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask] = val;
}
return;
@ -2095,7 +2115,12 @@ void ARM9Write16(u32 addr, u16 val)
case 0x00200000: GPU::WriteVRAM_BBG<u16>(addr, val); return;
case 0x00400000: GPU::WriteVRAM_AOBJ<u16>(addr, val); return;
case 0x00600000: GPU::WriteVRAM_BOBJ<u16>(addr, val); return;
default: GPU::WriteVRAM_LCDC<u16>(addr, val); return;
default:
#ifdef JIT_ENABLED
ARMJIT::InvalidateLCDCIfNecessary(addr);
#endif
GPU::WriteVRAM_LCDC<u16>(addr, val);
return;
}
case 0x07000000:
@ -2136,11 +2161,17 @@ void ARM9Write32(u32 addr, u32 val)
{
case 0x02000000:
*(u32*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateMainRAMIfNecessary(addr);
#endif
return ;
case 0x03000000:
if (SWRAM_ARM9)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateSWRAM9IfNecessary(addr);
#endif
*(u32*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask] = val;
}
return;
@ -2161,7 +2192,12 @@ void ARM9Write32(u32 addr, u32 val)
case 0x00200000: GPU::WriteVRAM_BBG<u32>(addr, val); return;
case 0x00400000: GPU::WriteVRAM_AOBJ<u32>(addr, val); return;
case 0x00600000: GPU::WriteVRAM_BOBJ<u32>(addr, val); return;
default: GPU::WriteVRAM_LCDC<u32>(addr, val); return;
default:
#ifdef JIT_ENABLED
ARMJIT::InvalidateLCDCIfNecessary(addr);
#endif
GPU::WriteVRAM_LCDC<u32>(addr, val);
return;
}
case 0x07000000:
@ -2426,30 +2462,38 @@ u32 ARM7Read32(u32 addr)
void ARM7Write8(u32 addr, u8 val)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateByAddr7(addr);
#endif
switch (addr & 0xFF800000)
{
case 0x02000000:
case 0x02800000:
*(u8*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateMainRAMIfNecessary(addr);
#endif
return;
case 0x03000000:
if (SWRAM_ARM7)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateSWRAM7IfNecessary(addr);
#endif
*(u8*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask] = val;
return;
}
else
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
#endif
*(u8*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
}
case 0x03800000:
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
#endif
*(u8*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
@ -2459,6 +2503,9 @@ void ARM7Write8(u32 addr, u8 val)
case 0x06000000:
case 0x06800000:
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WVRAMIfNecessary(addr);
#endif
GPU::WriteVRAM_ARM7<u8>(addr, val);
return;
@ -2489,30 +2536,38 @@ void ARM7Write8(u32 addr, u8 val)
void ARM7Write16(u32 addr, u16 val)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateByAddr7(addr);
#endif
switch (addr & 0xFF800000)
{
case 0x02000000:
case 0x02800000:
*(u16*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateMainRAMIfNecessary(addr);
#endif
return;
case 0x03000000:
if (SWRAM_ARM7)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateSWRAM7IfNecessary(addr);
#endif
*(u16*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask] = val;
return;
}
else
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
#endif
*(u16*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
}
case 0x03800000:
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
#endif
*(u16*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
@ -2530,6 +2585,9 @@ void ARM7Write16(u32 addr, u16 val)
case 0x06000000:
case 0x06800000:
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WVRAMIfNecessary(addr);
#endif
GPU::WriteVRAM_ARM7<u16>(addr, val);
return;
@ -2562,30 +2620,38 @@ void ARM7Write16(u32 addr, u16 val)
void ARM7Write32(u32 addr, u32 val)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateByAddr7(addr);
#endif
switch (addr & 0xFF800000)
{
case 0x02000000:
case 0x02800000:
*(u32*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
ARMJIT::InvalidateMainRAMIfNecessary(addr);
#endif
return;
case 0x03000000:
if (SWRAM_ARM7)
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateSWRAM7IfNecessary(addr);
#endif
*(u32*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask] = val;
return;
}
else
{
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
#endif
*(u32*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
}
case 0x03800000:
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
#endif
*(u32*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
@ -2604,6 +2670,9 @@ void ARM7Write32(u32 addr, u32 val)
case 0x06000000:
case 0x06800000:
#ifdef JIT_ENABLED
ARMJIT::InvalidateARM7WVRAMIfNecessary(addr);
#endif
GPU::WriteVRAM_ARM7<u32>(addr, val);
return;

9
src/NDS.h
View File

@ -80,7 +80,7 @@ enum
IRQ_IPCSendDone,
IRQ_IPCRecv,
IRQ_CartSendDone, // TODO: less misleading name
IRQ_CartIREQMC, // IRQ triggered by game cart (example: Pokémon Typing Adventure, BT controller)
IRQ_CartIREQMC, // IRQ triggered by game cart (example: Pok<EFBFBD>mon Typing Adventure, BT controller)
IRQ_GXFIFO,
IRQ_LidOpen,
IRQ_SPI,
@ -163,6 +163,13 @@ extern u16 ARM7BIOSProt;
extern u8 MainRAM[0x1000000];
extern u32 MainRAMMask;
extern u8 SharedWRAM[0x8000];
extern u8* SWRAM_ARM9;
extern u8* SWRAM_ARM7;
extern u32 SWRAM_ARM9Mask;
extern u32 SWRAM_ARM7Mask;
extern u8 ARM7WRAM[0x10000];
extern u32 KeyInput;