Connor McLaughlin
|
da0ad66080
|
GTE: Implement DPCL instruction
|
2019-09-27 23:44:33 +10:00 |
|
Connor McLaughlin
|
a479d820d4
|
CPU: Delay interrupts if the instruction in the pipeline is a TE instruction
|
2019-09-27 23:43:52 +10:00 |
|
Connor McLaughlin
|
e8cd174732
|
GTE: Implement DPCT
|
2019-09-27 22:57:07 +10:00 |
|
Connor McLaughlin
|
fc74d08641
|
GTE: Add some missing flag clear/updates
|
2019-09-27 22:48:56 +10:00 |
|
Connor McLaughlin
|
390639e795
|
GPU: Implement line rendering
|
2019-09-27 22:45:57 +10:00 |
|
Connor McLaughlin
|
f2a3629016
|
GPU: Support displaying only active region
|
2019-09-27 22:10:25 +10:00 |
|
Connor McLaughlin
|
c0a3a4176d
|
GPU: Enable batching of polygons with the different texture pages
|
2019-09-27 21:20:35 +10:00 |
|
Connor McLaughlin
|
69f6788f9f
|
GPU: Show stats from previous frame if no rendering occured
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2019-09-27 21:20:20 +10:00 |
|
Connor McLaughlin
|
c02cbc57e8
|
GPU: Properly handle semitransparent pixels
|
2019-09-27 17:40:26 +10:00 |
|
Connor McLaughlin
|
40d2497087
|
GPU: Fix incorrect palette used on some polygons
|
2019-09-27 16:17:09 +10:00 |
|
Connor McLaughlin
|
7ec3343ee6
|
Timers: Minor fixes
|
2019-09-27 00:08:36 +10:00 |
|
Connor McLaughlin
|
792ec27b1a
|
GPU: Improve batching by sampling a VRAM copy
|
2019-09-26 23:33:20 +10:00 |
|
Connor McLaughlin
|
332b5481e8
|
common: Log bad shaders to disk
|
2019-09-26 23:32:56 +10:00 |
|
Connor McLaughlin
|
b75674b149
|
SDL: Fix FPS counter disappearing behind menu
|
2019-09-26 23:31:44 +10:00 |
|
Connor McLaughlin
|
e9bb3d79b8
|
SDL: Add a shoddy FPS counter
|
2019-09-26 21:44:02 +10:00 |
|
Connor McLaughlin
|
2a63dbce64
|
GPU: Add stats interface
|
2019-09-26 14:03:32 +10:00 |
|
Connor McLaughlin
|
27cf3c99ac
|
GTE: Fix incorrect source in MVMVA
|
2019-09-26 13:43:41 +10:00 |
|
Connor McLaughlin
|
4d1837acb1
|
GTE: Special case for RTPS
|
2019-09-26 02:43:28 +10:00 |
|
Connor McLaughlin
|
d885abc528
|
GTE: More cleanups
|
2019-09-26 01:40:55 +10:00 |
|
Connor McLaughlin
|
f704d8fc63
|
GTE: Cleanup
|
2019-09-26 01:39:35 +10:00 |
|
Connor McLaughlin
|
ea3ba8b342
|
GPU: Various fixes (textures, blending)
|
2019-09-26 00:15:21 +10:00 |
|
Connor McLaughlin
|
767e8f08e0
|
CDROM: Move pregap handling to image class
|
2019-09-26 00:15:06 +10:00 |
|
Connor McLaughlin
|
ba67f69c2a
|
GTE: Implement NCCS/NCCT/NCDT/DPCS
|
2019-09-25 20:24:50 +10:00 |
|
Connor McLaughlin
|
b9b286e93d
|
GPU: Fix shader compile error on Intel
|
2019-09-25 20:24:19 +10:00 |
|
Connor McLaughlin
|
c18597c3bf
|
GTE: Implement unverified MVMVA
|
2019-09-25 15:58:33 +10:00 |
|
Connor McLaughlin
|
3df7b22c37
|
GTE: Fix NCDS
|
2019-09-25 15:40:08 +10:00 |
|
Connor McLaughlin
|
607cd4d3e4
|
CDROM: Stub out Setfilter
|
2019-09-25 00:44:41 +10:00 |
|
Connor McLaughlin
|
9359d0778e
|
Clean up memory access handlers, reduce template specializations
|
2019-09-25 00:36:24 +10:00 |
|
Connor McLaughlin
|
4aca52cdf4
|
CPU: Silence some debug spam
|
2019-09-24 23:56:30 +10:00 |
|
Connor McLaughlin
|
6aa36c2ead
|
SPU: Hook up DMA reads/writes to RAM
|
2019-09-24 23:55:57 +10:00 |
|
Connor McLaughlin
|
575a3b36f5
|
CDROM: Store the image path/current lba as part of the save state
|
2019-09-24 23:55:34 +10:00 |
|
Connor McLaughlin
|
1276241622
|
SPU: Create stub needed for DMA to work
|
2019-09-24 23:44:38 +10:00 |
|
Connor McLaughlin
|
7a413b4031
|
CDROM: Proper handling of request register
|
2019-09-24 21:39:38 +10:00 |
|
Connor McLaughlin
|
4bb8fb211d
|
DMA: Delay transfer/interrupt
|
2019-09-24 21:39:13 +10:00 |
|
Connor McLaughlin
|
4cc83e2228
|
DMA: Implement interrupts
|
2019-09-24 19:43:10 +10:00 |
|
Connor McLaughlin
|
db777fdabb
|
CDROM: Various fixes
|
2019-09-24 01:33:18 +10:00 |
|
Connor McLaughlin
|
1f13c4ad2c
|
Pad: Fix long transmit delay breaking other things
|
2019-09-24 01:31:17 +10:00 |
|
Connor McLaughlin
|
d65c9b3592
|
CDROM: Read timing and demute command, seek on ReadN
|
2019-09-23 23:31:51 +10:00 |
|
Connor McLaughlin
|
20f14688ca
|
System: Support loading expansion ROMs
|
2019-09-23 01:38:21 +10:00 |
|
Connor McLaughlin
|
5d1c12c9ad
|
Pad: Fix timing issues w/ BIOS
|
2019-09-23 01:25:58 +10:00 |
|
Connor McLaughlin
|
734d1a7ee1
|
InterruptController: Masked interrupts are still set in the status register
|
2019-09-23 01:24:36 +10:00 |
|
Connor McLaughlin
|
fbd7fcec48
|
GTE: Implement NCDS (but incorrectly)
|
2019-09-22 21:41:11 +10:00 |
|
Connor McLaughlin
|
f2d62fcce0
|
CDROM: Hack timings to get further with booting
|
2019-09-22 21:40:44 +10:00 |
|
Connor McLaughlin
|
c772047715
|
GTE: Add AVSZ3/AVSZ4
|
2019-09-22 20:38:11 +10:00 |
|
Connor McLaughlin
|
005b06ae0c
|
GTE: More implementation work, Reg+NCLIP+STR tests passing
|
2019-09-22 17:33:11 +10:00 |
|
Connor McLaughlin
|
3fb08a72a4
|
CDROM: Hack around missing pregap in images
|
2019-09-22 02:32:45 +10:00 |
|
Connor McLaughlin
|
948ac50020
|
CPU: Refactoring, implement LWC/SWC
|
2019-09-22 02:06:47 +10:00 |
|
Connor McLaughlin
|
2875a22987
|
CDROM: Reads appear to be functioning
|
2019-09-22 01:12:16 +10:00 |
|
Connor McLaughlin
|
c988af453c
|
Refactor timing to allow sync/updates in the middle of a slice
|
2019-09-21 01:24:33 +10:00 |
|
Connor McLaughlin
|
ad316162f3
|
Basic timer implementation
|
2019-09-20 23:40:19 +10:00 |