ShuriZma
/
bsnes
mirror of https://github.com/bsnes-emu/bsnes.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
861 Commits 1 Branch 122 Tags 59 MiB
Commit Graph

67 Commits

Author SHA1 Message Date
Rob Loach ec41e87cf1
Update logic behind params 2018-10-11 22:39:43 -04:00
Rob Loach b8825127fd
Fix parentheses around ‘+’ in operand of ‘&’ 
```
Core/z80_cpu.c: In function ‘add_hl_rr’:
Core/z80_cpu.c:341:31: error: suggest parentheses around ‘+’ in operand of ‘&’ [-Werror=parentheses]
     if ( ((unsigned long) hl) + ((unsigned long) rr) & 0x10000) {
          ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~
```
 2018-10-11 22:37:26 -04:00
Maximilian Mader a36dd791ec
Rewrite the DAA instruction 2018-07-22 18:37:34 +02:00
Lior Halphon f3437d7cc0 Added todo 2018-07-03 23:47:50 +03:00
Lior Halphon 45c73e0175 Replaced the is_cgb bool with a more future compatible model enum. Removed the GB_init_cgb API and replaced it with an extended GB_init and GB_switch_model_and_reset APIs that now receive a model parameter. Increased the struct version. 2018-06-16 13:59:33 +03:00
Lior Halphon 593cb7c107 Pixel accurate emulation of Prehistorik Man on a CGB-CPU-E 2018-06-08 18:44:03 +03:00
Lior Halphon ca01ff6f79 Finally, perfect emulation of the STAT write bug. 2018-06-08 17:16:15 +03:00
Lior Halphon 0481ff9af5 Whoops 2018-06-04 01:52:24 +03:00
Lior Halphon 6532aef089 Correct emulation of the DMG stat write bug 2018-05-26 18:06:40 +03:00
Lior Halphon 855ffb490a A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge. 2018-05-25 23:42:36 +03:00
Lior Halphon 249acb04cc Verified some timings on a DMG. Fixed palette write conflict timing (Although the fix kind of implies time traveling). Closes #65 2018-05-16 00:59:11 +03:00
Lior Halphon 1fcde88d8a Improved accuracy of the halt bug 2018-05-12 22:13:52 +03:00
Lior Halphon 713dc02e46 A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54 2018-05-11 12:38:55 +03:00
Lior Halphon af3554c1d1 More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB) 2018-04-27 13:40:39 +03:00
Lior Halphon be9df4d658 Added mechanism to handle MMIO read/write conflicts. Fixes #65 2018-04-14 17:57:00 +03:00
Lior Halphon 2c6f7906c5 Make multi-byte opcodes trigger the OAM bug when they increase PC 2018-04-14 15:32:55 +03:00
Lior Halphon 84aa06aba5 Clean up OAM bug code 2018-04-14 13:35:16 +03:00
Lior Halphon d667d87bbe Refactor CPU code so handling access conflicts is possible 2018-04-14 13:25:55 +03:00
Lior Halphon f1ec42d4ba H/GDMA was 4 times faster than it should have been. Made it also more accurate. Fixes #56 2018-04-13 14:41:39 +03:00
Lior Halphon a9fbbd3894 Merge branch 'master' of https://github.com/LIJI32/SameBoy 2018-03-29 21:07:04 +03:00
Lior Halphon e380a00b67 Fixed another timing regression with the CB opcodes 2018-03-29 21:06:53 +03:00
Kyle Swanson 7ffe132e79 fix typo 2018-03-28 21:38:48 -07:00
Lior Halphon f5493e023d Fixed a timing regression in the CB opcodes 2018-03-27 20:21:24 +03:00
Lior Halphon 7543461c24 Increasing PC in OAM triggers the OAM bug 2018-03-27 16:36:39 +03:00
Lior Halphon 4986930511 Mostly complete emulation of the OAM bug. Passes oam_bug-2. 2018-03-27 15:46:00 +03:00
Lior Halphon 9093f22293 More accurate emulation of the OAM bug 2018-03-24 14:46:51 +03:00
Lior Halphon d343152fca Basic emulation of the OAM bug 2018-03-24 00:32:19 +03:00
Lior Halphon 3e5e17d1a3 Fixed CB [hl] opcodes timings 2018-03-23 12:35:37 +03:00
Lior Halphon 3883b7d86a Merge branch 'master' into timing 
# Conflicts:
#	Core/display.c
#	Core/z80_cpu.c
 2018-03-19 23:46:33 +02:00
Lior Halphon b50c97f4a7 Prevent starting HDMA in the middle of an instruction, making both the CPU and DMA access memory at the same time. Closes #47 2018-03-19 20:01:31 +02:00
Lior Halphon 0dc30f081a CGB halt interrupt timing 2018-03-17 23:21:14 +02:00
Lior Halphon 544ca2be4c Changing the timings of memory writes so they’re not effectively one T-cycle late. This screws up APU’s cycle accuracy for now. 2018-03-05 21:17:37 +02:00
Lior Halphon b702d56547 Merge branch 'master' into timing 
# Conflicts:
#	Core/display.c
#	Core/z80_cpu.c
 2018-03-01 21:22:33 +02:00
Lior Halphon 90a943d05a Emulate an HDMA quirk required to properly emulate Aevilia 2018-02-25 22:32:41 +02:00
Lior Halphon ef670986c6 Rewrote PPU (currently only emulates DMG correctly) to use the new timing mechanism. Removed “future interrupts” (No longer required because SameBoy is now T-cycle based) 2018-02-25 00:48:45 +02:00
Lior Halphon 42ab746a66 Starting to remove the delayed interrupts hack – done for timer interrupt, broken for display interrupts 2018-02-23 15:33:44 +02:00
Lior Halphon 5974092c94 Bugfix 2018-02-20 23:04:35 +02:00
Lior Halphon 19c382c9e0 Fixed ei_sequence test 2017-12-03 21:07:34 +02:00
Lior Halphon be038dc8e7 Refinement to the last fix 2017-09-20 03:08:54 +03:00
Lior Halphon 57e7782ac4 Interrupt servicing is now more accurate. Fixes mooneye-gb’s ie_push (all models) and Pinball Deluxe (!!!) for CGB mode 2017-09-20 02:49:45 +03:00
Lior Halphon 14f267b4fa Another whoops 2017-09-09 19:31:05 +03:00
Lior Halphon 1e90400916 Reimplemented delayed/future interrupts, currently correct only for CGB. 2017-09-09 13:32:12 +03:00
Lior Halphon 0f643e01b7 Removing the delayed interrupt mechanism, research is not complete enough for implementation 2017-09-08 12:58:35 +03:00
Lior Halphon 54eb51d8db Refined timer interrupt timing 2017-09-02 22:08:20 +03:00
nattthebear eb7492c6c6 Fix undefined behavior (sequence point modification). GCC 4.6.4 compiles the code incorrectly without this fix. 2017-07-16 21:08:07 -04:00
Lior Halphon a925ef130d Stabilizing API: New joypad, debugger and reset APIs; internal APIs and direct struct access are no longer available without defining GB_INTERNAL. The SDL port uses the new “public” APIs, as well as most of the non-debug Cocoa code. 2017-04-17 20:16:17 +03:00
Lior Halphon 399e88d5fe STAT timing and LCD interrupts rewritten, should be more accurate. 2017-02-19 02:22:50 +02:00
Lior Halphon 74d00b84b7 Treat STOP as a 2-byte instruction 2017-02-17 00:21:02 +02:00
Lior Halphon 3fbc2c5716 DI should not be delayed. 2017-02-15 19:04:53 +02:00
Lior Halphon 2d51d13479 Various optimizations 2016-10-22 02:18:29 +03:00