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58 Commits

Author SHA1 Message Date
Lior Halphon 4c05ebcea6 Redo the volume envelope with better timings, locking emulation and zombie mode edge cases. Fixes #344 2021-02-25 15:43:38 +02:00
Lior Halphon 393269ae1f Emulate volume envelope locking 2021-02-22 13:48:56 +02:00
Lior Halphon c0582fd994 More accurate emulation of NR10 writes 2021-01-09 00:31:16 +02:00
Lior Halphon b54a72d9b9 Fixing a bug where where zero-shift sweep wouldn't tick 2021-01-02 14:56:45 +02:00
Lior Halphon 5c854dbdca Interference emulation 2020-12-31 00:07:04 +02:00
Lior Halphon 4f408eae7c Whoops 2020-12-12 18:13:55 +02:00
Lior Halphon 7de6194e28 Redo channel 4's timing accurately, emulate NR43 write quirks 2020-12-12 16:02:25 +02:00
Lior Halphon 1baa0446a9 More sweep improvements 2020-12-01 22:37:13 +02:00
Lior Halphon 74cf452a48 Further accuracy improvements to sweep; passes Blargg's APU tests again, this time for real 2020-12-01 14:17:35 +02:00
Lior Halphon 0485124076 Redo channel 1 sweep based on DMG schematics; emulates two newly discovered behaviors and also fixes #309 2020-11-28 19:31:25 +02:00
Lior Halphon 3cba3e8e27 Emulate CGB-C PCM read glitch, fix a potential noise volume envelope bug 2020-05-10 00:37:52 +03:00
Jakub Kądziołka 67d5a53503
Spell "length" properly 2020-02-27 18:11:10 +01:00
Lior Halphon 103caa56e1 Allow displaying borders outside of SGB emulation, including borrowing SGB border. Allow not displaying SGB borders. (Todo: libretro support) 2020-02-08 13:28:46 +02:00
Lior Halphon b806ae4e82 Fix #228 2020-02-01 23:36:16 +02:00
Lior Halphon 143e1f88a8 There’s not reason it must be an integer 2019-11-03 22:02:33 +02:00
Lior Halphon dee29c118c Added GB_set_sample_rate_by_clocks API, split SGB_NO_SFC into PAL and NTSC; now they report the correct clock rate. 2019-10-08 15:10:24 +03:00
Lior Halphon e268efefef Redesign and reimplement the audio API, let the frontends handle more stuff. Probably affects #161 2019-06-15 23:22:27 +03:00
Lior Halphon 9d8adbb581 This is not correct, this bug only affects the PCM registers and not actual output. Currently not emulated at all. 2019-06-07 18:37:19 +03:00
Lior Halphon 85c43fa81f Fixed Channel 3’s first sample behavior, update analog characteristic to more realistic values. Fixes #177 2019-05-25 19:12:09 +03:00
ISSOtm 40f83c8f25 Add APU-related debugger commands 
This change includes making one of the APU functions public
 2019-05-15 12:45:51 +02:00
Lior Halphon 4051f190a5 Cache cycles_per_sample to avoid FP arithmetic 2019-01-01 00:42:40 +02:00
Lior Halphon 94136f5741 Adjust DAC attributes to fix LADX’s crackling audio (Fixes #125) while keeping Cannon Fodder’s buzzing reasonable (Proper audio measurements still required) 2018-11-10 19:14:18 +02:00
Lior Halphon 64922fff4b Fixed a bug where channels 1 and 2 would start playing earlier than they should have if NRx4 was written to twice. Fixes #86. 2018-10-29 00:44:43 +02:00
Lior Halphon 3035f43428 Emulation of DAC charging, Fixes #46, #85, #88 and #89 2018-10-19 23:53:01 +03:00
Lior Halphon 324201f336 Correct emulation of switching the DACs on and off. Fixes #100 and #87 2018-10-17 20:35:29 +03:00
Lior Halphon dc5cb71c22 Emulate CGB-C’s quirky LFSR function 2018-07-04 21:55:12 +03:00
Lior Halphon f64da1864f APU glitch: When turning the APU on while DIV's bit 4 (or 5 in double speed mode), the first DIV/APU event is skipped. 2018-06-09 15:11:20 +03:00
Lior Halphon 80c92daacd Include cleanup (#73) 2018-05-27 19:30:23 +03:00
Lior Halphon 9802ca41dd Components not affected by CGB’s double speed mode now operate in 8MHz mode to theoretically make advance_cycles(gb, 1) safe. 2018-02-20 21:17:12 +02:00
Lior Halphon f79af39ea2 More accurate emulation of the APU’s analog characteristics 2018-02-16 18:01:50 +02:00
Lior Halphon fc35111ae7 Corrected the emulated DAC’s range 2018-02-16 01:26:37 +02:00
Lior Halphon 81f808e184 Refinements for the Wii U port 2018-02-10 15:02:22 +02:00
radius 217e9787bd change MAX_CH_AMP on WiiU 2018-02-07 15:28:30 -05:00
Lior Halphon a1af4c59ca Fixed NR51 volume levels (They’re 1-8, not 0-7) 2018-01-06 11:58:49 +02:00
Lior Halphon dc59fdf40e Highpass filter in SDL 2017-12-23 22:11:53 +02:00
Lior Halphon 8f4cd5c412 Corrected behavior for channel 1 and 2 restart 2017-09-22 02:04:29 +03:00
Lior Halphon 2ca550273a Fixed dmg_sound-5 2017-09-21 18:18:10 +03:00
Lior Halphon 8d011ca4b9 Accuracy improvements (Sweep) 2017-08-15 22:05:20 +03:00
Lior Halphon d04aaddcbd Added highpass filter 2017-08-15 21:59:11 +03:00
Lior Halphon 4b8be255ce Fixed some channel 4 delays, documented a not currently emulated timing quirk. 2017-08-12 19:50:39 +03:00
Lior Halphon 066efab985 In DMG mode, the length registers are not affected by turning the APU on and off. Why? Why not! 2017-08-11 22:23:03 +03:00
Lior Halphon 0e22ad8eb1 Noise channel support 2017-08-11 17:57:08 +03:00
Lior Halphon 1a8bcd314d Accuracy improvements to sweeping (Still not complete though, more research needed) 2017-08-10 19:42:23 +03:00
Lior Halphon ab5611119a Accuracy improvements, especially to the length control 2017-08-02 21:14:23 +03:00
Lior Halphon d65c2247e5 Added channel 1 and 2, fixed accuracy issues with channel 3 2017-07-27 23:11:33 +03:00
Lior Halphon 2936f7fa57 Fixed channel 3 counter behavior, verified with new tests. The DIV register ticks the APU at 512Hz. 2017-07-22 19:51:11 +03:00
Lior Halphon a19ee1e5e0 2MHz audio downscaling support. Implemented NR50 and NR51. 2017-07-21 23:17:48 +03:00
Lior Halphon baccf336d7 Complete rewrite of the APU. Channel 3 is complete and passes all the relevant tests from blargg’s suite, as well as PCM34-based tests. Actual sound output is basic and limited, though. 2017-07-21 19:06:55 +03:00
Lior Halphon 00623d4eea - Added audio supersampling support to greatly improve audio quality. 
- Fixed a bug where low sampling rate or disabled sound resulted in wrong APU behavior.
- Added API to get the current number of pending samples.
- This change broke save state compatibility with v0.8 and older
Closes #8.
 2017-05-12 17:11:55 +03:00
Lior Halphon 3feaeb153e New turbo related APIs, Quick Look no longer requires GB_INTERNAL 2017-04-19 21:55:58 +03:00