-Set the pending cycles for setting Sr1 to 14934 - 3791 instead of adding it. This working makes NO sense in my opinion, and I'm sure it will break as the number of interrupts increases, but for now, it matches up.
The newest issue is reading PSG registers which have not been set. Cool, expecting this to work without doing anything would be silly, so I've gotten somewhere!
-Cleanup.
-Added "Total Executed Cycles" to the log.
-By observing the aforementioned data, I realized that the docs probably meant to say 14934 instead of 14394.
--By adjusting this...TITLE SCREEN!
--Still, there are definitely discrepancies with the log that imply that I'm far from done.
-Enabled ANDR and XOR because they were executed during the title sequence, though it's hard to tell if it should at this point.
--Haven't done anything with the flags because I don't know what they are supposed to do yet.
--Speedy Gonzales v2 doesn't sync after being converted, but I don't think that's my fault.
-Flags and other data will be parsed soon.
--Did the same for the PSG because why not.
-Discovered that the Commando HLT happens after the CPU goes idle, so there's no point in further investigating the issue until I emulate that.
-Parsed the BACKTAB cards for the STIC's Draw().
-Attempted to draw the screen using the aforementioned cards.
--I'm only trying to apply color to the foreground.
---Instead of converting the FG color to RGBA, I'm making it all white for now.
--There's clearly some sanity to what's being drawn, so I think each 8x8 card is being drawn in the right place.
--I think the next step is trying to make each individual card draw properly.
--I believe the algorithm for populating the FrameBuffer is VERY inefficient in the way it accesses memory. Will need some suggestions as to how I can rewrite this.
--VirtualHeight / Width will be useful due to how the scanlines are doubled on TVs, but for now, I will just be drawing to scale.
-Enabled XOR@, SAR, and COMR. Advanced Dungeons & Dragons provided more test cases.
-Noticed that Commando, as well as some other games, triggers a HLT. This should be looked into later.
--This number is fairly arbitrary, and I don't know why it works, but for now, it does.
--The values of INTRM don't match up exactly, but I think this is mostly a logging issue, though I still need to look into this.
-Fixed the Overflow Flag calculation.
--My original formula didn't compare the signs of the operands.
--It always needs to use the original operands, not the 2s complement one.
--As such, a result parameter has been added.
-Fixed the detection of a double swap, shift, and rotate in the related instructions. Ironically, I shifted one too many bits in my detection.
-Masked the result of left shifts and rotates to 0xFFFF so that the flags are calculated properly.
-Made RSWD (un)set the right flags.
-Enabled GSWD, MVI, SARC, CMP@, ADD, SUB@, INCR, RRC, SLR, SLL, RLC, ADDR, SUBR, SLLC, CMPR, and RSWD.
-COMR, NEGR, ADCR, SAR, ANDR, SUB, AND, XOR, and XOR@ remain disabled as I have yet to hit any test cases for them.
At this point, IntelliHawk is executing instructions indefinitely with what seems to be perfect results! I think I'm ready to hook up the screen.
-Replaced subtraction with adding the 2s complement in instructions. That way, the Overflow Flag is calculated properly.
-Made it so that the masking of a result to 0xFFFF comes after calculating the Carry and Overflow Flags but before the Sign and Zero Flags.
-The CMPX instructions now use the aforementioned masking to properly calculate the Sign and Zero Flags even though the result doesn't actually get stored.
Thanks to this commit, IntelliHawk executes 1711 instructions properly. Next, it's supposed to take an Interrupt, which is bizarre because INTRM appears to be true at that point. This doesn't seem possible unless I am once again logging at the wrong time, hiding that the INTRM gets set to false before immediately switching back to true after taking the interrupt. Will look into this later.
-Added and Interrupted flag to make it so that interrupts only trigger once per falling edge.
-For now, interrupts take 28 cycles.
-Made it so that the STIC tracks Pending / Total Executed Cycles just like the CPU.
-Forwarded the cycles executed in the CPU to the STIC's Execute.
-SR1 is now inverted when there are no pending cycles.
--If SR1 is high, 14394 cycles are added to the pending cycles.
--If SR1 is low, 3791 cycles are added to the pending cycles.
--Not sure why the STIC has any connection to the SST, but the docs on the SST are virtually non-existent from what I could find.
--I took advantage of Func and Action instead of passing bool references to both devices. I think this makes sense.
-Added reset functions for both devices.
My comparison log for INTRM is still weird because it says it is true initially (Expected) and remains as such after the first instruction (A bit odd). I think this happens because the STIC is supposed to "tick" and shift SR1 to false immediately, but the STIC tick happens after the CPU tick, and the CPU tick is where the logging happens. I need to find a better place to put this logging, and I need to implement the STIC ticking for IntelliHawk. I'm not positive how to approach the latter issue as I assume a tick means one instruction execution, and my executions happen in a loop on the CPU, which has no reference to the STIC, so I'm not sure where this fits into the equation.
-I will now assume that 0x7000 is not mapped for the sake of continuing on. I will need to implement a mapper system shortly though.
--Did the same thing for 0x4800.
-AND@, MOVR, CMP enabled.
-Made the logging separator generate before an instruction instead of after the register states. This is quite petty, but I don't like the separator at the end of the file.
I hit an infinite loop, and I'm very very certain it's happening because I don't have an interrupt system yet. Time to stop avoiding that!
-Separated cartridge logic into a separate ICart named Cartridge.cs.
-Made WriteMemory return a bool to match ICart.Write. It currently returns true if either the cart or the core responded.
TODO: Parse the vanilla Intellivision ROM, which will hopefully include the read / writability of the data segments. adelikat seems to think that I just need to send the bytes to $5000, but I'm not convinced.
-Made it so that the indirect ops other than MVO@ decrement R6 when it's the mem address. Indirect write means writing to a register apparently, so maybe the documentation don't contradict itself.
-Fixed my disassembly of branch; I wasn't thinking in hexadecimal. >_<
-Subtracted 1 from the negated offset when branching in reverse. The next op is "BNEQ $FFFC".
adelikat