Add unmanaged version of 6502X core. The core it self is nearly exactly a copy+paste job from the C# one; most things map over exactly. A strange and abusive p/invoke setup is required to realize a performance gain; see code for details. Seems to be worth a bit more than 20% overall speed for me. Core is savestate compatible with managed 6502X. slight modifications to existing API has been made to support the new cpu. also included is a test module that runs both cores together, savestating every cycle to check for sameness. Core should fit in Atari, although that hasn't been done yet. For the moment, tracelog and disassemble are broken, but they'll be back soon.
This commit is contained in:
goyuken
parent
27bcfcff55
commit
cd2ff4ed63
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@ -386,6 +386,8 @@
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<Compile Include="CPUs\MOS 6502X\Disassembler.cs" />
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<Compile Include="CPUs\MOS 6502X\Execute.cs" />
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<Compile Include="CPUs\MOS 6502X\MOS6502X.cs" />
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<Compile Include="CPUs\MOS 6502X\MOS6502XDouble.cs" />
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<Compile Include="CPUs\MOS 6502X\MOS6502XNative.cs" />
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<Compile Include="CPUs\Native68000\Musashi.cs" />
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<Compile Include="CPUs\x86\Disassembler.cs" />
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<Compile Include="CPUs\x86\Execute.cs" />
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@ -291,7 +291,51 @@ namespace BizHawk.Emulation.CPUs.M6502
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/*VOP_RESET*/ new Uop[] { Uop.FetchDummy, Uop.FetchDummy, Uop.PushDummy, Uop.PushDummy, Uop.PushP_Reset, Uop.FetchPCLVector, Uop.FetchPCHVector, Uop.End_SuppressInterrupt },
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/*VOP_Fetch1_NoInterrupt*/ new Uop[] { Uop.Fetch1_Real },
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};
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/*
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static MOS6502X()
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{
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using (System.IO.StreamWriter sw = new System.IO.StreamWriter("UopEnum.h"))
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{
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sw.WriteLine("// AUTOGENERATED");
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sw.WriteLine("#ifndef UOPENUM_H");
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sw.WriteLine("#define UOPENUM_H");
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sw.WriteLine("enum Uop {");
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foreach (var v in Enum.GetValues(typeof(Uop)))
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{
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//sw.WriteLine("#define Uop_{0} {1}", (Uop)v, (int)v);
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sw.WriteLine("\tUop_{0}, ", (Uop)v);
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}
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sw.WriteLine("};");
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sw.WriteLine("#endif // UOPENUM_H");
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}
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using (System.IO.StreamWriter sw = new System.IO.StreamWriter("UopTable.cpp"))
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{
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sw.WriteLine("// AUTOGENERATED");
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sw.WriteLine("#include \"UopEnum.h\"");
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int max = 0;
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foreach (var a in Microcode)
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if (a.Length > max)
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max = a.Length;
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sw.WriteLine("const Uop Microcode[{0}][{1}] = {{", Microcode.Length, max);
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for (int i = 0; i < Microcode.Length; i++)
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{
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sw.Write("\t{");
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for (int j = 0; j < Microcode[i].Length; j++)
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{
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sw.Write("Uop_{0}", Microcode[i][j]);
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if (j < Microcode[i].Length - 1)
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sw.Write(", ");
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}
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sw.WriteLine("},");
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}
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sw.WriteLine("};");
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}
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}
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*/
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enum Uop
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{
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//sometimes i used this as a marker for unsupported instructions, but it is very inconsistent
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@ -6,7 +6,7 @@ namespace BizHawk.Emulation.CPUs.M6502
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{
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public sealed partial class MOS6502X
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{
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public MOS6502X()
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public MOS6502X(Action<System.Runtime.InteropServices.GCHandle> DisposeBuilder = null)
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{
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Reset();
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}
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@ -168,6 +168,19 @@ namespace BizHawk.Emulation.CPUs.M6502
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public Func<ushort, byte> DummyReadMemory;
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public Action<ushort, byte> WriteMemory;
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public void SetCallbacks
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(
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Func<ushort, byte> ReadMemory,
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Func<ushort, byte> DummyReadMemory,
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Action<ushort, byte> WriteMemory,
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Action<System.Runtime.InteropServices.GCHandle> DisposeBuilder
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)
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{
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this.ReadMemory = ReadMemory;
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this.DummyReadMemory = DummyReadMemory;
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this.WriteMemory = WriteMemory;
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}
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public ushort ReadWord(ushort address)
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{
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byte l = ReadMemory(address);
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@ -0,0 +1,209 @@
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.IO;
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using System.Collections.Concurrent;
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namespace BizHawk.Emulation.CPUs.M6502
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{
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/// <summary>
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/// maintains a managed 6502X and an unmanaged 6502X, running them alongside and ensuring consistency
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/// by taking savestates every cycle (!). slow.
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/// </summary>
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public class MOS6502XDouble
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{
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MOS6502X m;
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MOS6502X_CPP n;
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public MOS6502XDouble(Action<System.Runtime.InteropServices.GCHandle> DisposeBuilder)
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{
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m = new MOS6502X(DisposeBuilder);
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n = new MOS6502X_CPP(DisposeBuilder);
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BCD_Enabled = true;
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m.SetCallbacks(
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delegate(ushort addr)
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{
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byte ret = ReadMemory(addr);
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reads.Enqueue(ret);
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return ret;
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},
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delegate(ushort addr)
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{
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byte ret = DummyReadMemory(addr);
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reads.Enqueue(ret);
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return ret;
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},
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delegate(ushort addr, byte value)
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{
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writes.Enqueue(value);
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WriteMemory(addr, value);
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}, DisposeBuilder);
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n.SetCallbacks(
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delegate(ushort addr)
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{
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if (reads.Count > 0)
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return reads.Dequeue();
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else
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{
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PreCrash();
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throw new Exception("native did extra read!");
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}
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},
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delegate(ushort addr)
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{
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if (reads.Count > 0)
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return reads.Dequeue();
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else
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{
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PreCrash();
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throw new Exception("native did extra read!");
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}
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},
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delegate(ushort addr, byte value)
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{
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if (writes.Count > 0)
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{
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byte test = writes.Dequeue();
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if (test != value)
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{
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PreCrash();
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throw new Exception(string.Format("writes were different! managed {0} native {1}", test, value));
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}
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// ignore because the write already happened
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}
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else
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{
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PreCrash();
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throw new Exception("native did extra write!");
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}
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}, DisposeBuilder);
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SyncUp();
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}
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Queue<byte> reads = new Queue<byte>();
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Queue<byte> writes = new Queue<byte>();
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private bool _BCD_Enabled;
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public bool BCD_Enabled { get { return _BCD_Enabled; } set { _BCD_Enabled = value; m.BCD_Enabled = value; n.BCD_Enabled = value; } }
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public bool debug { get; private set; }
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public bool throw_unhandled { get; private set; }
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public byte A { get; private set; }
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public byte X { get; private set; }
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public byte Y { get; private set; }
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byte _P;
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public byte P { get { return _P; } set { _P = value; m.P = value; n.P = value; SyncUp(); } }
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ushort _PC;
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public ushort PC { get { return _PC; } set { _PC = value; m.PC = value; n.PC = value; SyncUp(); } }
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byte _S;
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public byte S { get { return _S; } set { _S = value; m.S = value; n.S = value; SyncUp(); } }
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bool _IRQ;
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public bool IRQ { get { return _IRQ; } set { _IRQ = value; m.IRQ = value; n.IRQ = value; } }
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bool _NMI;
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public bool NMI { get { return _NMI; } set { _NMI = value; m.NMI = value; n.NMI = value; } }
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public int TotalExecutedCycles { get; private set; }
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public Func<ushort, byte> ReadMemory; //{ set { m.ReadMemory = value; n.ReadMemory = value; } }
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public Func<ushort, byte> DummyReadMemory; //{ set { m.DummyReadMemory = value; n.DummyReadMemory = value; } }
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public Action<ushort, byte> WriteMemory; //{ set { m.WriteMemory = value; n.WriteMemory = value; } }
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public void SetCallbacks
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(
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Func<ushort, byte> ReadMemory,
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Func<ushort, byte> DummyReadMemory,
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Action<ushort, byte> WriteMemory,
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Action<System.Runtime.InteropServices.GCHandle> DisposeBuilder
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)
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{
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this.ReadMemory = ReadMemory;
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this.DummyReadMemory = DummyReadMemory;
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this.WriteMemory = WriteMemory;
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}
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string oldleft = "";
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string oldright = "";
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void PreCrash()
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{
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System.Windows.Forms.MessageBox.Show(string.Format("about to crash! cached:\n==managed==\n{0}\n==native==\n{1}\n", oldleft, oldright));
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}
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void TestQueue()
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{
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if (reads.Count > 0)
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{
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PreCrash();
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throw new Exception("managed did extra read!");
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}
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if (writes.Count > 0)
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{
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PreCrash();
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throw new Exception("managed did extra write!");
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}
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}
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void SyncUp()
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{
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TestQueue();
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StringWriter sm = new StringWriter();
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Serializer ssm = new Serializer(sm);
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m.SyncState(ssm);
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sm.Flush();
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StringWriter sn = new StringWriter();
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Serializer ssn = new Serializer(sn);
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n.SyncState(ssn);
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sn.Flush();
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string sssm = sm.ToString();
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string sssn = sn.ToString();
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if (sssm != sssn)
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{
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PreCrash();
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throw new Exception(string.Format("save mismatch!\n==managed==\n{0}\n==native==\n{1}\n", sssm, sssn));
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}
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A = m.A;
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X = m.X;
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Y = m.Y;
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_P = m.P;
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_PC = m.PC;
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_S = m.S;
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_IRQ = m.IRQ;
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_NMI = m.NMI;
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oldleft = sssm;
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oldright = sssn;
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}
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public string State()
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{
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SyncUp();
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return m.State();
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}
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public void NESSoftReset()
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{
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m.NESSoftReset();
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n.NESSoftReset();
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SyncUp();
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}
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public void ExecuteOne()
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{
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m.ExecuteOne();
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n.ExecuteOne();
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SyncUp();
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}
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public void SyncState(Serializer ser)
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{
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SyncUp();
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m.SyncState(ser);
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}
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public string Disassemble(ushort pc, out int bytesToAdvance) { bytesToAdvance = 1; return "FOOBAR"; }
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}
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}
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@ -0,0 +1,221 @@
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.Runtime.InteropServices;
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namespace BizHawk.Emulation.CPUs.M6502
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{
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public static class MOS6502X_DLL
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{
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[UnmanagedFunctionPointer(System.Runtime.InteropServices.CallingConvention.Cdecl)]
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public delegate byte ReadMemoryD(ushort addr);
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[UnmanagedFunctionPointer(System.Runtime.InteropServices.CallingConvention.Cdecl)]
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public delegate void WriteMemoryD(ushort addr, byte value);
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[DllImport("MOS6502XNative.dll", CallingConvention = CallingConvention.Cdecl)]
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public static extern IntPtr Create();
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[DllImport("MOS6502XNative.dll", CallingConvention = CallingConvention.Cdecl)]
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public static extern void Destroy(IntPtr ptr);
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[DllImport("MOS6502XNative.dll", CallingConvention = CallingConvention.ThisCall, EntryPoint = "?Reset@MOS6502X@@QAEXXZ")]
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public static extern void Reset(IntPtr ptr);
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[DllImport("MOS6502XNative.dll", CallingConvention = CallingConvention.ThisCall, EntryPoint = "?NESSoftReset@MOS6502X@@QAEXXZ")]
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public static extern void NESSoftReset(IntPtr ptr);
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[DllImport("MOS6502XNative.dll", CallingConvention = CallingConvention.ThisCall, EntryPoint = "?ExecuteOne@MOS6502X@@QAEXXZ")]
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public static extern void ExecuteOne(IntPtr ptr);
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[DllImport("MOS6502XNative.dll", CallingConvention = CallingConvention.ThisCall, EntryPoint = "?SetTrampolines@MOS6502X@@QAEXP6AEG@Z0P6AXGE@Z@Z")]
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public static extern void SetTrampolines(IntPtr ptr, ReadMemoryD Read, ReadMemoryD DummyRead, WriteMemoryD Write);
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}
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/// <summary>
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/// MOS6502X core in unmanaged code
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/// </summary>
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[StructLayout(LayoutKind.Explicit)]
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public class MOS6502X_CPP
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{
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/*
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* In order to get anywhere near usable performance, the class is cleared of all unblittable types,
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* set up with identical memory order to a C++ class, and then GC pinned for the duration. A
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* naive pinvoke attempt will produce 1/7th the performance of this.
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*/
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// these are aliased to a C++ class, so don't move them
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#region c++ alias
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// C# bool is not blittable!
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[FieldOffset(0x00), MarshalAs(UnmanagedType.U1)]
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byte _BCD_Enabled;
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[FieldOffset(0x01), MarshalAs(UnmanagedType.U1)]
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public byte debug;
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[FieldOffset(0x02), MarshalAs(UnmanagedType.U1)]
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public byte throw_unhandled;
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[FieldOffset(0x03)]
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public byte A;
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[FieldOffset(0x04)]
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public byte X;
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[FieldOffset(0x05)]
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public byte Y;
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[FieldOffset(0x06)]
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public byte P;
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[FieldOffset(0x08)]
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public ushort PC;
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[FieldOffset(0x0a)]
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public byte S;
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[FieldOffset(0x0b), MarshalAs(UnmanagedType.U1)]
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byte _IRQ;
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[FieldOffset(0x0c), MarshalAs(UnmanagedType.U1)]
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byte _NMI;
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[FieldOffset(0x10)]
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public int TotalExecutedCycles;
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// delegates are not blittable, so pretend they aren't there
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[FieldOffset(0x14)]
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IntPtr ZZZ000;
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//public MOS6502X_DLL.ReadMemoryD ReadMemory;
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[FieldOffset(0x18)]
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IntPtr ZZZ001;
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//public MOS6502X_DLL.ReadMemoryD DummyReadMemory;
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[FieldOffset(0x1c)]
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IntPtr ZZZ002;
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//public MOS6502X_DLL.WriteMemoryD WriteMemory;
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//opcode bytes.. theoretically redundant with the temp variables? who knows.
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[FieldOffset(0x20)]
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public int opcode;
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[FieldOffset(0x24)]
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public byte opcode2;
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[FieldOffset(0x25)]
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public byte opcode3;
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[FieldOffset(0x28)]
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public int ea;
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[FieldOffset(0x2c)]
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public int alu_temp; //cpu internal temp variables
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[FieldOffset(0x30)]
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public int mi; //microcode index
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[FieldOffset(0x34), MarshalAs(UnmanagedType.U1)]
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public byte iflag_pending; //iflag must be stored after it is checked in some cases (CLI and SEI).
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//tracks whether an interrupt condition has popped up recently.
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//not sure if this is real or not but it helps with the branch_irq_hack
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[FieldOffset(0x35), MarshalAs(UnmanagedType.U1)]
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public byte interrupt_pending;
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[FieldOffset(0x36), MarshalAs(UnmanagedType.U1)]
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public byte branch_irq_hack; //see Uop.RelBranch_Stage3 for more details
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#endregion
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[FieldOffset(0x48)]
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IntPtr pthis;
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// for fields which were converted from bool to byte, use props for backwards compatibility
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public bool IRQ { get { return _IRQ != 0; } set { _IRQ = (byte)(value ? 1 : 0); } }
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public bool NMI { get { return _NMI != 0; } set { _NMI = (byte)(value ? 1 : 0); } }
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public bool BCD_Enabled { get { return _BCD_Enabled != 0; } set { _BCD_Enabled = (byte)(value ? 1 : 0); } }
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public MOS6502X_CPP(Action<GCHandle> DisposeBuilder)
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{
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// this bit of foolery is only needed if you actually need to run the native-side constructor
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//IntPtr native = MOS6502X_DLL.Create();
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//if (native == null)
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// throw new Exception("Native constructor returned null!");
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var h = GCHandle.Alloc(this, GCHandleType.Pinned);
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pthis = h.AddrOfPinnedObject();
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// bad - use memcpy instead
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//Marshal.PtrToStructure(native, this);
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//MOS6502X_DLL.Destroy(native);
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BCD_Enabled = true;
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MOS6502X_DLL.Reset(pthis);
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DisposeBuilder(h);
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}
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public void Reset() { MOS6502X_DLL.Reset(pthis); }
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public void NESSoftReset() { MOS6502X_DLL.NESSoftReset(pthis); }
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public void ExecuteOne() { MOS6502X_DLL.ExecuteOne(pthis); }
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public string State() { return "FOOBAR"; } /*
|
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{
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int notused;
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string a = string.Format("{0:X4} {1:X2} {2} ", PC, ReadMemory(PC), Disassemble(PC, out notused)).PadRight(30);
|
||||
string b = string.Format("A:{0:X2} X:{1:X2} Y:{2:X2} P:{3:X2} SP:{4:X2} Cy:{5}", A, X, Y, P, S, TotalExecutedCycles);
|
||||
string val = a + b + " ";
|
||||
if (FlagN) val = val + "N";
|
||||
if (FlagV) val = val + "V";
|
||||
if (FlagT) val = val + "T";
|
||||
if (FlagB) val = val + "B";
|
||||
if (FlagD) val = val + "D";
|
||||
if (FlagI) val = val + "I";
|
||||
if (FlagZ) val = val + "Z";
|
||||
if (FlagC) val = val + "C";
|
||||
return val;
|
||||
}*/
|
||||
|
||||
// to maintain savestate compatibility, we have bytes that we serialize as bool
|
||||
static void SyncByteFakeBool(Serializer ser, string name, ref byte loc)
|
||||
{
|
||||
bool tmp = loc != 0;
|
||||
ser.Sync(name, ref tmp);
|
||||
loc = (byte)(tmp ? 1 : 0);
|
||||
}
|
||||
|
||||
public void SyncState(Serializer ser)
|
||||
{
|
||||
ser.BeginSection("MOS6502X");
|
||||
ser.Sync("A", ref A);
|
||||
ser.Sync("X", ref X);
|
||||
ser.Sync("Y", ref Y);
|
||||
ser.Sync("P", ref P);
|
||||
ser.Sync("PC", ref PC);
|
||||
ser.Sync("S", ref S);
|
||||
SyncByteFakeBool(ser, "NMI", ref _NMI);//ser.Sync("NMI", ref _NMI);
|
||||
SyncByteFakeBool(ser, "IRQ", ref _IRQ);//ser.Sync("IRQ", ref _IRQ);
|
||||
ser.Sync("TotalExecutedCycles", ref TotalExecutedCycles);
|
||||
ser.Sync("opcode", ref opcode);
|
||||
ser.Sync("opcode2", ref opcode2);
|
||||
ser.Sync("opcode3", ref opcode3);
|
||||
ser.Sync("ea", ref ea);
|
||||
ser.Sync("alu_temp", ref alu_temp);
|
||||
ser.Sync("mi", ref mi);
|
||||
SyncByteFakeBool(ser, "iflag_pending", ref iflag_pending); //ser.Sync("iflag_pending", ref iflag_pending);
|
||||
SyncByteFakeBool(ser, "interrupt_pending", ref interrupt_pending); //ser.Sync("interrupt_pending", ref interrupt_pending);
|
||||
SyncByteFakeBool(ser, "branch_irq_hack", ref branch_irq_hack); //ser.Sync("branch_irq_hack", ref branch_irq_hack);
|
||||
ser.EndSection();
|
||||
}
|
||||
|
||||
public string Disassemble(ushort pc, out int bytesToAdvance) { bytesToAdvance = 1; return "FOOBAR"; }
|
||||
|
||||
public void SetCallbacks
|
||||
(Func<ushort, byte> ReadMemory,
|
||||
Func<ushort, byte> DummyReadMemory,
|
||||
Action<ushort, byte> WriteMemory, Action<GCHandle> DisposeBuilder)
|
||||
{
|
||||
var d1 = new MOS6502X_DLL.ReadMemoryD(ReadMemory);
|
||||
var h1 = GCHandle.Alloc(d1);
|
||||
var d2 = new MOS6502X_DLL.ReadMemoryD(DummyReadMemory);
|
||||
var h2 = GCHandle.Alloc(d2);
|
||||
var d3 = new MOS6502X_DLL.WriteMemoryD(WriteMemory);
|
||||
var h3 = GCHandle.Alloc(d3);
|
||||
|
||||
MOS6502X_DLL.SetTrampolines(pthis, d1, d2, d3);
|
||||
DisposeBuilder(h1);
|
||||
DisposeBuilder(h2);
|
||||
DisposeBuilder(h3);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,80 @@
|
|||
#include "MOS6502X.h"
|
||||
|
||||
void MOS6502X::FetchDummy()
|
||||
{
|
||||
DummyReadMemory(PC);
|
||||
}
|
||||
|
||||
void MOS6502X::Reset()
|
||||
{
|
||||
A = 0;
|
||||
X = 0;
|
||||
Y = 0;
|
||||
P = 0;
|
||||
S = 0;
|
||||
PC = 0;
|
||||
TotalExecutedCycles = 0;
|
||||
mi = 0;
|
||||
opcode = 256;
|
||||
//MessageBox(NULL,L"Opcode set to 256", NULL, 0);
|
||||
iflag_pending = true;
|
||||
}
|
||||
|
||||
void MOS6502X::SetTrampolines(byte (__cdecl *ReadMemory)(ushort), byte (__cdecl *DummyReadMemory)(ushort), void (__cdecl *WriteMemory)(ushort, byte))
|
||||
{
|
||||
this->ReadMemory = ReadMemory;
|
||||
this->DummyReadMemory = DummyReadMemory;
|
||||
this->WriteMemory = WriteMemory;
|
||||
}
|
||||
|
||||
/*
|
||||
#include <string>
|
||||
#define SHOWRA(a) SHOWGA((int)(void *)(a) - ((int)(void *)cpu), #a)
|
||||
|
||||
void SHOWGA(int diff, const char *nom)
|
||||
{
|
||||
char buffra[24];
|
||||
std::sprintf(buffra, "%08xi", diff);
|
||||
MessageBoxA(NULL, buffra, nom, 0);
|
||||
}*/
|
||||
|
||||
void* Create()
|
||||
{
|
||||
MOS6502X* cpu = new MOS6502X();
|
||||
/*
|
||||
SHOWRA(&cpu->BCD_Enabled);
|
||||
SHOWRA(&cpu->debug);
|
||||
SHOWRA(&cpu->throw_unhandled);
|
||||
SHOWRA(&cpu->A);
|
||||
SHOWRA(&cpu->X);
|
||||
SHOWRA(&cpu->Y);
|
||||
SHOWRA(&cpu->P);
|
||||
SHOWRA(&cpu->PC);
|
||||
SHOWRA(&cpu->S);
|
||||
SHOWRA(&cpu->IRQ);
|
||||
SHOWRA(&cpu->NMI);
|
||||
SHOWRA(&cpu->TotalExecutedCycles);
|
||||
SHOWRA(&cpu->ReadMemory);
|
||||
SHOWRA(&cpu->DummyReadMemory);
|
||||
SHOWRA(&cpu->WriteMemory);
|
||||
SHOWRA(&cpu->opcode);
|
||||
SHOWRA(&cpu->opcode2);
|
||||
SHOWRA(&cpu->opcode3);
|
||||
SHOWRA(&cpu->ea);
|
||||
SHOWRA(&cpu->alu_temp);
|
||||
SHOWRA(&cpu->mi);
|
||||
SHOWRA(&cpu->iflag_pending);
|
||||
SHOWRA(&cpu->interrupt_pending);
|
||||
SHOWRA(&cpu->branch_irq_hack);
|
||||
*/
|
||||
|
||||
return (void *)cpu;
|
||||
}
|
||||
|
||||
void Destroy(void *ptr)
|
||||
{
|
||||
MOS6502X* cpu = (MOS6502X*) ptr;
|
||||
delete cpu;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#ifndef MOS6502X_H
|
||||
#define MOS6502X_H
|
||||
|
||||
#include "ints.h"
|
||||
|
||||
class MOS6502X
|
||||
{
|
||||
public:
|
||||
bool BCD_Enabled;
|
||||
bool debug;
|
||||
bool throw_unhandled;
|
||||
|
||||
byte A;
|
||||
byte X;
|
||||
byte Y;
|
||||
byte P;
|
||||
ushort PC;
|
||||
byte S;
|
||||
|
||||
bool IRQ;
|
||||
bool NMI;
|
||||
|
||||
int TotalExecutedCycles;
|
||||
|
||||
byte (__cdecl *ReadMemory)(ushort);
|
||||
byte (__cdecl *DummyReadMemory)(ushort);
|
||||
void (__cdecl *WriteMemory)(ushort, byte);
|
||||
|
||||
//opcode bytes.. theoretically redundant with the temp variables? who knows.
|
||||
int opcode;
|
||||
byte opcode2, opcode3;
|
||||
|
||||
int ea, alu_temp; //cpu internal temp variables
|
||||
int mi; //microcode index
|
||||
bool iflag_pending; //iflag must be stored after it is checked in some cases (CLI and SEI).
|
||||
|
||||
//tracks whether an interrupt condition has popped up recently.
|
||||
//not sure if this is real or not but it helps with the branch_irq_hack
|
||||
bool interrupt_pending;
|
||||
bool branch_irq_hack; //see Uop.RelBranch_Stage3 for more details
|
||||
|
||||
|
||||
__declspec(dllexport) void ExecuteOne();
|
||||
void FetchDummy();
|
||||
__declspec(dllexport) void Reset();
|
||||
__declspec(dllexport) void NESSoftReset();
|
||||
__declspec(dllexport) void SetTrampolines(byte (__cdecl *ReadMemory)(ushort), byte (__cdecl *DummyReadMemory)(ushort), void (__cdecl *WriteMemory)(ushort, byte));
|
||||
};
|
||||
|
||||
extern "C" __declspec(dllexport) void* __cdecl Create();
|
||||
extern "C" __declspec(dllexport) void __cdecl Destroy(void *);
|
||||
|
||||
#endif // MOS6502X_H
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
|
||||
Microsoft Visual Studio Solution File, Format Version 11.00
|
||||
# Visual Studio 2010
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MOS6502XNative", "MOS6502XNative.vcxproj", "{3F8F3D38-25DB-45C9-84C9-943D0368BF47}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Win32 = Debug|Win32
|
||||
Release|Win32 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{3F8F3D38-25DB-45C9-84C9-943D0368BF47}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{3F8F3D38-25DB-45C9-84C9-943D0368BF47}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{3F8F3D38-25DB-45C9-84C9-943D0368BF47}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{3F8F3D38-25DB-45C9-84C9-943D0368BF47}.Release|Win32.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
EndGlobalSection
|
||||
EndGlobal
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup Label="ProjectConfigurations">
|
||||
<ProjectConfiguration Include="Debug|Win32">
|
||||
<Configuration>Debug</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
<ProjectConfiguration Include="Release|Win32">
|
||||
<Configuration>Release</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
</ItemGroup>
|
||||
<PropertyGroup Label="Globals">
|
||||
<ProjectGuid>{3F8F3D38-25DB-45C9-84C9-943D0368BF47}</ProjectGuid>
|
||||
<Keyword>Win32Proj</Keyword>
|
||||
<RootNamespace>MOS6502XNative</RootNamespace>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
|
||||
<ConfigurationType>DynamicLibrary</ConfigurationType>
|
||||
<UseDebugLibraries>true</UseDebugLibraries>
|
||||
<CharacterSet>Unicode</CharacterSet>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
|
||||
<ConfigurationType>DynamicLibrary</ConfigurationType>
|
||||
<UseDebugLibraries>false</UseDebugLibraries>
|
||||
<WholeProgramOptimization>true</WholeProgramOptimization>
|
||||
<CharacterSet>Unicode</CharacterSet>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
|
||||
<ImportGroup Label="ExtensionSettings">
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<PropertyGroup Label="UserMacros" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<LinkIncremental>true</LinkIncremental>
|
||||
<CustomBuildAfterTargets>
|
||||
</CustomBuildAfterTargets>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<LinkIncremental>false</LinkIncremental>
|
||||
<CustomBuildAfterTargets>
|
||||
</CustomBuildAfterTargets>
|
||||
</PropertyGroup>
|
||||
<ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<ClCompile>
|
||||
<PrecompiledHeader>NotUsing</PrecompiledHeader>
|
||||
<WarningLevel>Level3</WarningLevel>
|
||||
<Optimization>Disabled</Optimization>
|
||||
<PreprocessorDefinitions>WIN32;_DEBUG;_WINDOWS;_USRDLL;MOS6502XNATIVE_EXPORTS;%(PreprocessorDefinitions)</PreprocessorDefinitions>
|
||||
</ClCompile>
|
||||
<Link>
|
||||
<SubSystem>Windows</SubSystem>
|
||||
<GenerateDebugInformation>true</GenerateDebugInformation>
|
||||
</Link>
|
||||
<PostBuildEvent>
|
||||
<Command>copy "$(TargetDir)$(TargetName).dll" "$(SolutionDir)..\..\..\..\BizHawk.MultiClient\output\dll\$(TargetName).dll"</Command>
|
||||
</PostBuildEvent>
|
||||
</ItemDefinitionGroup>
|
||||
<ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<ClCompile>
|
||||
<WarningLevel>Level3</WarningLevel>
|
||||
<PrecompiledHeader>NotUsing</PrecompiledHeader>
|
||||
<Optimization>MaxSpeed</Optimization>
|
||||
<FunctionLevelLinking>true</FunctionLevelLinking>
|
||||
<IntrinsicFunctions>true</IntrinsicFunctions>
|
||||
<PreprocessorDefinitions>WIN32;NDEBUG;_WINDOWS;_USRDLL;MOS6502XNATIVE_EXPORTS;%(PreprocessorDefinitions)</PreprocessorDefinitions>
|
||||
</ClCompile>
|
||||
<Link>
|
||||
<SubSystem>Windows</SubSystem>
|
||||
<GenerateDebugInformation>true</GenerateDebugInformation>
|
||||
<EnableCOMDATFolding>true</EnableCOMDATFolding>
|
||||
<OptimizeReferences>true</OptimizeReferences>
|
||||
</Link>
|
||||
<PostBuildEvent>
|
||||
<Command>copy "$(TargetDir)$(TargetName).dll" "$(SolutionDir)..\..\..\..\BizHawk.MultiClient\output\dll\$(TargetName).dll"</Command>
|
||||
</PostBuildEvent>
|
||||
</ItemDefinitionGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="ints.h" />
|
||||
<ClInclude Include="MOS6502X.h" />
|
||||
<ClInclude Include="UopEnum.h" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="Execute.cpp" />
|
||||
<ClCompile Include="MOS6502X.cpp" />
|
||||
<ClCompile Include="UopTable.cpp" />
|
||||
</ItemGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
</ImportGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup>
|
||||
<Filter Include="Source Files">
|
||||
<UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
|
||||
<Extensions>cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
|
||||
</Filter>
|
||||
<Filter Include="Header Files">
|
||||
<UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
|
||||
<Extensions>h;hpp;hxx;hm;inl;inc;xsd</Extensions>
|
||||
</Filter>
|
||||
<Filter Include="Resource Files">
|
||||
<UniqueIdentifier>{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}</UniqueIdentifier>
|
||||
<Extensions>rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms</Extensions>
|
||||
</Filter>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="UopEnum.h">
|
||||
<Filter>Header Files</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="MOS6502X.h">
|
||||
<Filter>Header Files</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="ints.h">
|
||||
<Filter>Header Files</Filter>
|
||||
</ClInclude>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="UopTable.cpp">
|
||||
<Filter>Source Files</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="Execute.cpp">
|
||||
<Filter>Source Files</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="MOS6502X.cpp">
|
||||
<Filter>Source Files</Filter>
|
||||
</ClCompile>
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
// AUTOGENERATED
|
||||
#ifndef UOPENUM_H
|
||||
#define UOPENUM_H
|
||||
enum Uop {
|
||||
Uop_Unsupported,
|
||||
Uop_Fetch1,
|
||||
Uop_Fetch1_Real,
|
||||
Uop_Fetch2,
|
||||
Uop_Fetch3,
|
||||
Uop_FetchDummy,
|
||||
Uop_NOP,
|
||||
Uop_JSR,
|
||||
Uop_IncPC,
|
||||
Uop_Abs_WRITE_STA,
|
||||
Uop_Abs_WRITE_STX,
|
||||
Uop_Abs_WRITE_STY,
|
||||
Uop_Abs_WRITE_SAX,
|
||||
Uop_Abs_READ_BIT,
|
||||
Uop_Abs_READ_LDA,
|
||||
Uop_Abs_READ_LDY,
|
||||
Uop_Abs_READ_ORA,
|
||||
Uop_Abs_READ_LDX,
|
||||
Uop_Abs_READ_CMP,
|
||||
Uop_Abs_READ_ADC,
|
||||
Uop_Abs_READ_CPX,
|
||||
Uop_Abs_READ_SBC,
|
||||
Uop_Abs_READ_AND,
|
||||
Uop_Abs_READ_EOR,
|
||||
Uop_Abs_READ_CPY,
|
||||
Uop_Abs_READ_NOP,
|
||||
Uop_Abs_READ_LAX,
|
||||
Uop_Abs_RMW_Stage4,
|
||||
Uop_Abs_RMW_Stage6,
|
||||
Uop_Abs_RMW_Stage5_INC,
|
||||
Uop_Abs_RMW_Stage5_DEC,
|
||||
Uop_Abs_RMW_Stage5_LSR,
|
||||
Uop_Abs_RMW_Stage5_ROL,
|
||||
Uop_Abs_RMW_Stage5_ASL,
|
||||
Uop_Abs_RMW_Stage5_ROR,
|
||||
Uop_Abs_RMW_Stage5_SLO,
|
||||
Uop_Abs_RMW_Stage5_RLA,
|
||||
Uop_Abs_RMW_Stage5_SRE,
|
||||
Uop_Abs_RMW_Stage5_RRA,
|
||||
Uop_Abs_RMW_Stage5_DCP,
|
||||
Uop_Abs_RMW_Stage5_ISC,
|
||||
Uop_JMP_abs,
|
||||
Uop_ZpIdx_Stage3_X,
|
||||
Uop_ZpIdx_Stage3_Y,
|
||||
Uop_ZpIdx_RMW_Stage4,
|
||||
Uop_ZpIdx_RMW_Stage6,
|
||||
Uop_ZP_WRITE_STA,
|
||||
Uop_ZP_WRITE_STX,
|
||||
Uop_ZP_WRITE_STY,
|
||||
Uop_ZP_WRITE_SAX,
|
||||
Uop_ZP_RMW_Stage3,
|
||||
Uop_ZP_RMW_Stage5,
|
||||
Uop_ZP_RMW_DEC,
|
||||
Uop_ZP_RMW_INC,
|
||||
Uop_ZP_RMW_ASL,
|
||||
Uop_ZP_RMW_LSR,
|
||||
Uop_ZP_RMW_ROR,
|
||||
Uop_ZP_RMW_ROL,
|
||||
Uop_ZP_RMW_SLO,
|
||||
Uop_ZP_RMW_RLA,
|
||||
Uop_ZP_RMW_SRE,
|
||||
Uop_ZP_RMW_RRA,
|
||||
Uop_ZP_RMW_DCP,
|
||||
Uop_ZP_RMW_ISC,
|
||||
Uop_ZP_READ_EOR,
|
||||
Uop_ZP_READ_BIT,
|
||||
Uop_ZP_READ_ORA,
|
||||
Uop_ZP_READ_LDA,
|
||||
Uop_ZP_READ_LDY,
|
||||
Uop_ZP_READ_LDX,
|
||||
Uop_ZP_READ_CPX,
|
||||
Uop_ZP_READ_SBC,
|
||||
Uop_ZP_READ_CPY,
|
||||
Uop_ZP_READ_NOP,
|
||||
Uop_ZP_READ_ADC,
|
||||
Uop_ZP_READ_AND,
|
||||
Uop_ZP_READ_CMP,
|
||||
Uop_ZP_READ_LAX,
|
||||
Uop_IdxInd_Stage3,
|
||||
Uop_IdxInd_Stage4,
|
||||
Uop_IdxInd_Stage5,
|
||||
Uop_IdxInd_Stage6_READ_ORA,
|
||||
Uop_IdxInd_Stage6_READ_SBC,
|
||||
Uop_IdxInd_Stage6_READ_LDA,
|
||||
Uop_IdxInd_Stage6_READ_EOR,
|
||||
Uop_IdxInd_Stage6_READ_CMP,
|
||||
Uop_IdxInd_Stage6_READ_ADC,
|
||||
Uop_IdxInd_Stage6_READ_AND,
|
||||
Uop_IdxInd_Stage6_READ_LAX,
|
||||
Uop_IdxInd_Stage6_WRITE_STA,
|
||||
Uop_IdxInd_Stage6_WRITE_SAX,
|
||||
Uop_IdxInd_Stage6_RMW,
|
||||
Uop_IdxInd_Stage7_RMW_SLO,
|
||||
Uop_IdxInd_Stage7_RMW_RLA,
|
||||
Uop_IdxInd_Stage7_RMW_SRE,
|
||||
Uop_IdxInd_Stage7_RMW_RRA,
|
||||
Uop_IdxInd_Stage7_RMW_ISC,
|
||||
Uop_IdxInd_Stage7_RMW_DCP,
|
||||
Uop_IdxInd_Stage8_RMW,
|
||||
Uop_AbsIdx_Stage3_X,
|
||||
Uop_AbsIdx_Stage3_Y,
|
||||
Uop_AbsIdx_Stage4,
|
||||
Uop_AbsIdx_WRITE_Stage5_STA,
|
||||
Uop_AbsIdx_WRITE_Stage5_SHY,
|
||||
Uop_AbsIdx_WRITE_Stage5_SHX,
|
||||
Uop_AbsIdx_WRITE_Stage5_ERROR,
|
||||
Uop_AbsIdx_READ_Stage4,
|
||||
Uop_AbsIdx_READ_Stage5_LDA,
|
||||
Uop_AbsIdx_READ_Stage5_CMP,
|
||||
Uop_AbsIdx_READ_Stage5_SBC,
|
||||
Uop_AbsIdx_READ_Stage5_ADC,
|
||||
Uop_AbsIdx_READ_Stage5_EOR,
|
||||
Uop_AbsIdx_READ_Stage5_LDX,
|
||||
Uop_AbsIdx_READ_Stage5_AND,
|
||||
Uop_AbsIdx_READ_Stage5_ORA,
|
||||
Uop_AbsIdx_READ_Stage5_LDY,
|
||||
Uop_AbsIdx_READ_Stage5_NOP,
|
||||
Uop_AbsIdx_READ_Stage5_LAX,
|
||||
Uop_AbsIdx_READ_Stage5_ERROR,
|
||||
Uop_AbsIdx_RMW_Stage5,
|
||||
Uop_AbsIdx_RMW_Stage7,
|
||||
Uop_AbsIdx_RMW_Stage6_ROR,
|
||||
Uop_AbsIdx_RMW_Stage6_DEC,
|
||||
Uop_AbsIdx_RMW_Stage6_INC,
|
||||
Uop_AbsIdx_RMW_Stage6_ASL,
|
||||
Uop_AbsIdx_RMW_Stage6_LSR,
|
||||
Uop_AbsIdx_RMW_Stage6_ROL,
|
||||
Uop_AbsIdx_RMW_Stage6_SLO,
|
||||
Uop_AbsIdx_RMW_Stage6_RLA,
|
||||
Uop_AbsIdx_RMW_Stage6_SRE,
|
||||
Uop_AbsIdx_RMW_Stage6_RRA,
|
||||
Uop_AbsIdx_RMW_Stage6_DCP,
|
||||
Uop_AbsIdx_RMW_Stage6_ISC,
|
||||
Uop_IncS,
|
||||
Uop_DecS,
|
||||
Uop_PushPCL,
|
||||
Uop_PushPCH,
|
||||
Uop_PushPCH_B,
|
||||
Uop_PushP,
|
||||
Uop_PullP,
|
||||
Uop_PullPCL,
|
||||
Uop_PullPCH_NoInc,
|
||||
Uop_PushA,
|
||||
Uop_PullA_NoInc,
|
||||
Uop_PullP_NoInc,
|
||||
Uop_PushP_BRK,
|
||||
Uop_PushP_NMI,
|
||||
Uop_PushP_IRQ,
|
||||
Uop_PushP_Reset,
|
||||
Uop_PushDummy,
|
||||
Uop_FetchPCLVector,
|
||||
Uop_FetchPCHVector,
|
||||
Uop_Imp_ASL_A,
|
||||
Uop_Imp_ROL_A,
|
||||
Uop_Imp_ROR_A,
|
||||
Uop_Imp_LSR_A,
|
||||
Uop_Imp_SEC,
|
||||
Uop_Imp_CLI,
|
||||
Uop_Imp_SEI,
|
||||
Uop_Imp_CLD,
|
||||
Uop_Imp_CLC,
|
||||
Uop_Imp_CLV,
|
||||
Uop_Imp_SED,
|
||||
Uop_Imp_INY,
|
||||
Uop_Imp_DEY,
|
||||
Uop_Imp_INX,
|
||||
Uop_Imp_DEX,
|
||||
Uop_Imp_TSX,
|
||||
Uop_Imp_TXS,
|
||||
Uop_Imp_TAX,
|
||||
Uop_Imp_TAY,
|
||||
Uop_Imp_TYA,
|
||||
Uop_Imp_TXA,
|
||||
Uop_Imm_CMP,
|
||||
Uop_Imm_ADC,
|
||||
Uop_Imm_AND,
|
||||
Uop_Imm_SBC,
|
||||
Uop_Imm_ORA,
|
||||
Uop_Imm_EOR,
|
||||
Uop_Imm_CPY,
|
||||
Uop_Imm_CPX,
|
||||
Uop_Imm_ANC,
|
||||
Uop_Imm_ASR,
|
||||
Uop_Imm_ARR,
|
||||
Uop_Imm_LXA,
|
||||
Uop_Imm_AXS,
|
||||
Uop_Imm_LDA,
|
||||
Uop_Imm_LDX,
|
||||
Uop_Imm_LDY,
|
||||
Uop_Imm_Unsupported,
|
||||
Uop_NZ_X,
|
||||
Uop_NZ_Y,
|
||||
Uop_NZ_A,
|
||||
Uop_RelBranch_Stage2_BNE,
|
||||
Uop_RelBranch_Stage2_BPL,
|
||||
Uop_RelBranch_Stage2_BCC,
|
||||
Uop_RelBranch_Stage2_BCS,
|
||||
Uop_RelBranch_Stage2_BEQ,
|
||||
Uop_RelBranch_Stage2_BMI,
|
||||
Uop_RelBranch_Stage2_BVC,
|
||||
Uop_RelBranch_Stage2_BVS,
|
||||
Uop_RelBranch_Stage2,
|
||||
Uop_RelBranch_Stage3,
|
||||
Uop_RelBranch_Stage4,
|
||||
Uop__Eor,
|
||||
Uop__Bit,
|
||||
Uop__Cpx,
|
||||
Uop__Cpy,
|
||||
Uop__Cmp,
|
||||
Uop__Adc,
|
||||
Uop__Sbc,
|
||||
Uop__Ora,
|
||||
Uop__And,
|
||||
Uop__Anc,
|
||||
Uop__Asr,
|
||||
Uop__Arr,
|
||||
Uop__Lxa,
|
||||
Uop__Axs,
|
||||
Uop_AbsInd_JMP_Stage4,
|
||||
Uop_AbsInd_JMP_Stage5,
|
||||
Uop_IndIdx_Stage3,
|
||||
Uop_IndIdx_Stage4,
|
||||
Uop_IndIdx_READ_Stage5,
|
||||
Uop_IndIdx_WRITE_Stage5,
|
||||
Uop_IndIdx_WRITE_Stage6_STA,
|
||||
Uop_IndIdx_WRITE_Stage6_SHA,
|
||||
Uop_IndIdx_READ_Stage6_LDA,
|
||||
Uop_IndIdx_READ_Stage6_CMP,
|
||||
Uop_IndIdx_READ_Stage6_ORA,
|
||||
Uop_IndIdx_READ_Stage6_SBC,
|
||||
Uop_IndIdx_READ_Stage6_ADC,
|
||||
Uop_IndIdx_READ_Stage6_AND,
|
||||
Uop_IndIdx_READ_Stage6_EOR,
|
||||
Uop_IndIdx_READ_Stage6_LAX,
|
||||
Uop_IndIdx_RMW_Stage5,
|
||||
Uop_IndIdx_RMW_Stage6,
|
||||
Uop_IndIdx_RMW_Stage7_SLO,
|
||||
Uop_IndIdx_RMW_Stage7_RLA,
|
||||
Uop_IndIdx_RMW_Stage7_SRE,
|
||||
Uop_IndIdx_RMW_Stage7_RRA,
|
||||
Uop_IndIdx_RMW_Stage7_ISC,
|
||||
Uop_IndIdx_RMW_Stage7_DCP,
|
||||
Uop_IndIdx_RMW_Stage8,
|
||||
Uop_End,
|
||||
Uop_End_ISpecial,
|
||||
Uop_End_BranchSpecial,
|
||||
Uop_End_SuppressInterrupt,
|
||||
};
|
||||
extern const Uop Microcode[264][8];
|
||||
#endif // UOPENUM_H
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
// AUTOGENERATED
|
||||
#include "UopEnum.h"
|
||||
const Uop Microcode[264][8] = {
|
||||
{Uop_Fetch2, Uop_PushPCH, Uop_PushPCL, Uop_PushP_BRK, Uop_FetchPCLVector, Uop_FetchPCHVector, Uop_End_SuppressInterrupt},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_ORA, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_RMW, Uop_IdxInd_Stage7_RMW_SLO, Uop_IdxInd_Stage8_RMW, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_ORA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_ASL, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_SLO, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_FetchDummy, Uop_PushP, Uop_End},
|
||||
{Uop_Imm_ORA, Uop_End},
|
||||
{Uop_Imp_ASL_A, Uop_End},
|
||||
{Uop_Imm_ANC, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_ORA, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_ASL, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_SLO, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BPL, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_ORA, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_RMW_Stage5, Uop_IndIdx_RMW_Stage6, Uop_IndIdx_RMW_Stage7_SLO, Uop_IndIdx_RMW_Stage8, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_ORA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_ASL, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_SLO, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Imp_CLC, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_ORA, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_SLO, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_ORA, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_ASL, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_SLO, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_NOP, Uop_PushPCH, Uop_PushPCL, Uop_JSR, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_AND, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_RMW, Uop_IdxInd_Stage7_RMW_RLA, Uop_IdxInd_Stage8_RMW, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_BIT, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_AND, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_ROL, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_RLA, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_FetchDummy, Uop_IncS, Uop_PullP_NoInc, Uop_End_ISpecial},
|
||||
{Uop_Imm_AND, Uop_End},
|
||||
{Uop_Imp_ROL_A, Uop_End},
|
||||
{Uop_Imm_ANC, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_BIT, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_AND, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_ROL, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_RLA, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BMI, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_AND, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_RMW_Stage5, Uop_IndIdx_RMW_Stage6, Uop_IndIdx_RMW_Stage7_RLA, Uop_IndIdx_RMW_Stage8, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_AND, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_ROL, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_RLA, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Imp_SEC, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_AND, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_RLA, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_AND, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_ROL, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_RLA, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_FetchDummy, Uop_IncS, Uop_PullP, Uop_PullPCL, Uop_PullPCH_NoInc, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_EOR, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_RMW, Uop_IdxInd_Stage7_RMW_SRE, Uop_IdxInd_Stage8_RMW, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_EOR, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_LSR, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_SRE, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_FetchDummy, Uop_PushA, Uop_End},
|
||||
{Uop_Imm_EOR, Uop_End},
|
||||
{Uop_Imp_LSR_A, Uop_End},
|
||||
{Uop_Imm_ASR, Uop_End},
|
||||
{Uop_Fetch2, Uop_JMP_abs, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_EOR, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_LSR, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_SRE, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BVC, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_EOR, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_RMW_Stage5, Uop_IndIdx_RMW_Stage6, Uop_IndIdx_RMW_Stage7_SRE, Uop_IndIdx_RMW_Stage8, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_EOR, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_LSR, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_SRE, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Imp_CLI, Uop_End_ISpecial},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_EOR, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_SRE, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_EOR, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_LSR, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_SRE, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_FetchDummy, Uop_IncS, Uop_PullPCL, Uop_PullPCH_NoInc, Uop_IncPC, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_ADC, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_RMW, Uop_IdxInd_Stage7_RMW_RRA, Uop_IdxInd_Stage8_RMW, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_ADC, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_ROR, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_RRA, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_FetchDummy, Uop_IncS, Uop_PullA_NoInc, Uop_End},
|
||||
{Uop_Imm_ADC, Uop_End},
|
||||
{Uop_Imp_ROR_A, Uop_End},
|
||||
{Uop_Imm_ARR, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_AbsInd_JMP_Stage4, Uop_AbsInd_JMP_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_ADC, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_ROR, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_RRA, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BVS, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_ADC, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_RMW_Stage5, Uop_IndIdx_RMW_Stage6, Uop_IndIdx_RMW_Stage7_RRA, Uop_IndIdx_RMW_Stage8, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_ADC, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_ROR, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_RRA, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Imp_SEI, Uop_End_ISpecial},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_ADC, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_RRA, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_ADC, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_ROR, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_RRA, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Imm_Unsupported, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_WRITE_STA, Uop_End},
|
||||
{Uop_Imm_Unsupported, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_WRITE_SAX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_WRITE_STY, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_WRITE_STA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_WRITE_STX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_WRITE_SAX, Uop_End},
|
||||
{Uop_Imp_DEY, Uop_End},
|
||||
{Uop_Imm_Unsupported, Uop_End},
|
||||
{Uop_Imp_TXA, Uop_End},
|
||||
{Uop_Imm_Unsupported, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_WRITE_STY, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_WRITE_STA, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_WRITE_STX, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_WRITE_SAX, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BCC, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_WRITE_Stage5, Uop_IndIdx_WRITE_Stage6_STA, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_WRITE_Stage5, Uop_IndIdx_WRITE_Stage6_SHA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_WRITE_STY, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_WRITE_STA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_Y, Uop_ZP_WRITE_STX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_Y, Uop_ZP_WRITE_SAX, Uop_End},
|
||||
{Uop_Imp_TYA, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_WRITE_Stage5_STA, Uop_End},
|
||||
{Uop_Imp_TXS, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_WRITE_Stage5_ERROR, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_WRITE_Stage5_SHY, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_WRITE_Stage5_STA, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_WRITE_Stage5_SHX, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_WRITE_Stage5_SHY, Uop_End},
|
||||
{Uop_Imm_LDY, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_LDA, Uop_End},
|
||||
{Uop_Imm_LDX, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_LAX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_LDY, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_LDA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_LDX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_LAX, Uop_End},
|
||||
{Uop_Imp_TAY, Uop_End},
|
||||
{Uop_Imm_LDA, Uop_End},
|
||||
{Uop_Imp_TAX, Uop_End},
|
||||
{Uop_Imm_LXA, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_LDY, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_LDA, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_LDX, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_LAX, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BCS, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_LDA, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_LAX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_LDY, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_LDA, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_Y, Uop_ZP_READ_LDX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_Y, Uop_ZP_READ_LAX, Uop_End},
|
||||
{Uop_Imp_CLV, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_LDA, Uop_End},
|
||||
{Uop_Imp_TSX, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_ERROR, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_LDY, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_LDA, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_LDX, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_LAX, Uop_End},
|
||||
{Uop_Imm_CPY, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_CMP, Uop_End},
|
||||
{Uop_Imm_Unsupported, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_RMW, Uop_IdxInd_Stage7_RMW_DCP, Uop_IdxInd_Stage8_RMW, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_CPY, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_CMP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_DEC, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_DCP, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Imp_INY, Uop_End},
|
||||
{Uop_Imm_CMP, Uop_End},
|
||||
{Uop_Imp_DEX, Uop_End},
|
||||
{Uop_Imm_AXS, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_CPY, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_CMP, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_DEC, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_DCP, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BNE, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_CMP, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_RMW_Stage5, Uop_IndIdx_RMW_Stage6, Uop_IndIdx_RMW_Stage7_DCP, Uop_IndIdx_RMW_Stage8, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_CMP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_DEC, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_DCP, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Imp_CLD, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_CMP, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_DCP, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_CMP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_DEC, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_DCP, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Imm_CPX, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_READ_SBC, Uop_End},
|
||||
{Uop_Imm_Unsupported, Uop_End},
|
||||
{Uop_Fetch2, Uop_IdxInd_Stage3, Uop_IdxInd_Stage4, Uop_IdxInd_Stage5, Uop_IdxInd_Stage6_RMW, Uop_IdxInd_Stage7_RMW_ISC, Uop_IdxInd_Stage8_RMW, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_CPX, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_READ_SBC, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_INC, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZP_RMW_Stage3, Uop_ZP_RMW_ISC, Uop_ZP_RMW_Stage5, Uop_End},
|
||||
{Uop_Imp_INX, Uop_End},
|
||||
{Uop_Imm_SBC, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Imm_SBC, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_CPX, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_READ_SBC, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_INC, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_Fetch3, Uop_Abs_RMW_Stage4, Uop_Abs_RMW_Stage5_ISC, Uop_Abs_RMW_Stage6, Uop_End},
|
||||
{Uop_RelBranch_Stage2_BEQ, Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_READ_Stage5, Uop_IndIdx_READ_Stage6_SBC, Uop_End},
|
||||
{Uop_End},
|
||||
{Uop_Fetch2, Uop_IndIdx_Stage3, Uop_IndIdx_Stage4, Uop_IndIdx_RMW_Stage5, Uop_IndIdx_RMW_Stage6, Uop_IndIdx_RMW_Stage7_ISC, Uop_IndIdx_RMW_Stage8, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZP_READ_SBC, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_INC, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Fetch2, Uop_ZpIdx_Stage3_X, Uop_ZpIdx_RMW_Stage4, Uop_ZP_RMW_ISC, Uop_ZpIdx_RMW_Stage6, Uop_End},
|
||||
{Uop_Imp_SED, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_SBC, Uop_End},
|
||||
{Uop_FetchDummy, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_Y, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_ISC, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_NOP, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_READ_Stage4, Uop_AbsIdx_READ_Stage5_SBC, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_INC, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch2, Uop_AbsIdx_Stage3_X, Uop_AbsIdx_Stage4, Uop_AbsIdx_RMW_Stage5, Uop_AbsIdx_RMW_Stage6_ISC, Uop_AbsIdx_RMW_Stage7, Uop_End},
|
||||
{Uop_Fetch1},
|
||||
{Uop_RelBranch_Stage3, Uop_End_BranchSpecial},
|
||||
{Uop_RelBranch_Stage4, Uop_End},
|
||||
{Uop_End_SuppressInterrupt},
|
||||
{Uop_FetchDummy, Uop_FetchDummy, Uop_PushPCH, Uop_PushPCL, Uop_PushP_NMI, Uop_FetchPCLVector, Uop_FetchPCHVector, Uop_End_SuppressInterrupt},
|
||||
{Uop_FetchDummy, Uop_FetchDummy, Uop_PushPCH, Uop_PushPCL, Uop_PushP_IRQ, Uop_FetchPCLVector, Uop_FetchPCHVector, Uop_End_SuppressInterrupt},
|
||||
{Uop_FetchDummy, Uop_FetchDummy, Uop_PushDummy, Uop_PushDummy, Uop_PushP_Reset, Uop_FetchPCLVector, Uop_FetchPCHVector, Uop_End_SuppressInterrupt},
|
||||
{Uop_Fetch1_Real},
|
||||
};
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef INTS_H
|
||||
#define INTS_H
|
||||
|
||||
typedef unsigned char byte;
|
||||
typedef unsigned short ushort;
|
||||
typedef signed char sbyte;
|
||||
|
||||
#endif
|
||||
|
|
@ -11,7 +11,12 @@ namespace BizHawk.Emulation.Consoles.Nintendo
|
|||
public partial class NES : IEmulator
|
||||
{
|
||||
//hardware/state
|
||||
public MOS6502X cpu;
|
||||
// any of the 3 cpus are drop in replacements
|
||||
//public MOS6502X cpu;
|
||||
public MOS6502X_CPP cpu;
|
||||
//public MOS6502XDouble cpu;
|
||||
// dispose list as the native core can't keep track of its own stuff
|
||||
List<System.Runtime.InteropServices.GCHandle> DisposeList = new List<System.Runtime.InteropServices.GCHandle>();
|
||||
int cpu_accumulate; //cpu timekeeper
|
||||
public PPU ppu;
|
||||
public APU apu;
|
||||
|
|
@ -45,6 +50,12 @@ namespace BizHawk.Emulation.Consoles.Nintendo
|
|||
{
|
||||
if (magicSoundProvider != null) magicSoundProvider.Dispose();
|
||||
magicSoundProvider = null;
|
||||
if (DisposeList != null)
|
||||
{
|
||||
foreach (var h in DisposeList)
|
||||
h.Free();
|
||||
DisposeList = null;
|
||||
}
|
||||
}
|
||||
|
||||
class MagicSoundProvider : ISoundProvider, IDisposable
|
||||
|
|
@ -101,13 +112,12 @@ namespace BizHawk.Emulation.Consoles.Nintendo
|
|||
}
|
||||
MagicSoundProvider magicSoundProvider;
|
||||
|
||||
|
||||
public void HardReset()
|
||||
{
|
||||
cpu = new MOS6502X();
|
||||
cpu.DummyReadMemory = ReadMemory;
|
||||
cpu.ReadMemory = ReadMemory;
|
||||
cpu.WriteMemory = WriteMemory;
|
||||
//cpu = new MOS6502X((h) => DisposeList.Add(h));
|
||||
cpu = new MOS6502X_CPP((h) => DisposeList.Add(h));
|
||||
//cpu = new MOS6502XDouble((h) => DisposeList.Add(h));
|
||||
cpu.SetCallbacks(ReadMemory, ReadMemory, WriteMemory, (h) => DisposeList.Add(h));
|
||||
cpu.BCD_Enabled = false;
|
||||
ppu = new PPU(this);
|
||||
ram = new byte[0x800];
|
||||
|
|
|
|||
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Reference in New Issue