ca90b90698
MOS/Via.cs - comment out unused variable
2020-03-19 10:33:08 -05:00
606c3bf1c2
use more advanced language features in Emulation.Cores ( #1852 )
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* Use expression bodies in Emulation.Cores, and a few other misc cleanups
* remove unused usings in Emulation.Common
* cleanups in Tables_Direct.cs
* some cleanups in nes boards - redundant code
* remove some redundant array initializers in Emulation.Cores
* cleanup AmstradCPC.Controllers
* use object initializers in a lot of places
* nes mappers - remove disch's notes comments in favor of the nesdev wiki link
* cleanup CdtConverter.cs, mostly use of object initializers
* remove redundant .ToString() calls in Emulation.Cores
* using var in Emulation.Cores
* AmstradCPC/ZXSpectrum - simplify some linq, tabs instead of spaces, a few other misc cleanups
* Use null-propagation in Emulation.Cores
2020-02-17 16:54:51 -06:00
969642b6c7
add Get/SetCpuFlagsAndRegisters to MOS6502X, and have cores point to that, instead of the same boilerplate in each core
2020-02-16 17:44:52 -06:00
b2a3477f52
Enable SA1123 and fix noncompliance
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"Do not place regions within elements"
2020-01-25 18:06:56 +10:00
6f3f01125c
Enable SA1504 and fix noncompliance
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"All accessors should be single-line or multi-line"
i.e. no block form on one line
2020-01-25 14:56:56 +10:00
fec63fb66a
Spaces -> tabs, fix mixed newlines.
2019-11-03 20:58:36 -05:00
c956b5993b
Small FFT change I had stashed.
2019-10-21 00:10:28 -04:00
1e5fe55f30
C64: Don't reallocate the SID filter buffer every time (purely perf)
2019-07-19 19:09:08 -05:00
a119420c79
C64: VC count enable seems to need to be delayed by 1 cycle after badline
...
- which doesn't affect normal operation
- which DOES affect VSP
2019-07-14 20:22:07 -05:00
4d6ed8d6c8
C64: Savestate should include the new variables
2019-07-14 16:32:53 -05:00
8e8d3a6a1b
C64: Writes to some registers on the VIC in phase 2 by the CPU should only take effect on the following cycle
2019-07-14 10:44:56 -05:00
e8902b829a
C64: Apparently the 6502X core needs interrupts delayed by a cycle, do that with IRQ and NMI
2019-07-14 10:43:52 -05:00
3bbfb98fc2
C64: Split out VIC IRQ delays
2019-07-13 19:28:44 -05:00
154eefd2ad
C64: Give BA/IRQ counting another go, seems to resolve many issues
2019-07-13 16:51:30 -05:00
db38d5e65b
C64: Try counting IRQ and BA correctly
2019-07-13 15:28:57 -05:00
f22c9b7abd
C64: CPU reads open bus when !AEC is asserted
2019-07-13 15:25:40 -05:00
894adbb610
C64: Remove an unused variable
2019-07-13 15:02:18 -05:00
76679bc8bc
C64: Use the correct background color in bitmapped modes for 0
2019-07-13 15:01:11 -05:00
bd20b355f0
C64: Writing to CPU port writes open bus data to 00/01
2019-07-13 14:06:23 -05:00
cae3340946
C64: No need to expose these with the CPU link in place
2019-07-13 12:53:34 -05:00
3369dbf43f
C64: IRQ is implemented as a delay line; no delay added (yet)
2019-07-13 12:51:39 -05:00
d39f3e2e61
6502X: pending IRQs are not delayed when !RDY is asserted
2019-07-13 12:31:09 -05:00
d62f2ac3fe
C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite)
2019-07-13 01:41:58 -05:00
e6871b2cc3
C64: Move VIC raster IRQ to phase 1
2019-07-13 00:27:08 -05:00
dbf6b39e7f
C64: Split out VIC phase1/phase2
2019-07-12 23:51:55 -05:00
0a7dc52aa0
C64: BA and raster IRQ cleanup
2019-07-09 22:41:12 -05:00
3a135c7c26
C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ
2019-07-09 21:40:03 -05:00
e63d10b608
C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA
2019-07-09 20:55:14 -05:00
b471fdc692
C64: The CPU can trigger VIC badlines on its own (needed for VSP)
2019-07-09 20:53:54 -05:00
2abe832289
C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does
2019-07-09 20:52:51 -05:00
a8fd85157c
VIC: Use correct color mapping for non-multicolor bitmap mode
2019-07-09 08:02:55 -05:00
83b6553749
VIC: Respect idle state background color registers, plus black in undocumented gfx mode
2019-07-09 06:58:13 -05:00
89fa153477
VIC: Resolve background color registers separately to color matrix memory
2019-07-09 06:55:55 -05:00
9f733d3e7a
VIC: More accurate pixel pipeline
2019-07-09 05:26:26 -05:00
6ed11de85b
C64: Soft/Hard reset: it's about time
2019-07-06 01:19:58 -05:00
400b04b690
C64: CIA was sometimes delaying too long to fire interrupts by 1 cycle.
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- This could have implications for existing TASes (!)
2019-07-05 23:59:01 -05:00
69f8b143a3
C64: Foreground pixels are black when VIC is in idle state.
2019-07-05 21:05:38 -05:00
49b613962e
C64: Fix a typo disabling voice 3 when high pass filter is set
2019-07-04 17:32:35 -05:00
f45e934fec
C64: Reset the SID filter on hard reset.
2019-07-04 17:24:22 -05:00
579ffe5c25
C64: Had the flag with the wrong polarity. Thanks, C64Anabalt.
2019-07-04 14:20:12 -05:00
691577499f
C64: When a sprite is eligible for display, initialize it with the correct crunch state based on Y expansion
2019-07-04 14:12:46 -05:00
36ac592193
C64: Individual IRQ flags for S/S or S/D collisions are always set even if not eligible to assert IRQ externally
2019-07-04 13:59:41 -05:00
5c9445fb96
C64: Reuse some local memory in the sprite renderer.
2019-07-04 12:47:09 -05:00
2c804cab34
C64: Fix a function ambiguity in the CIA class.
2019-07-04 00:51:19 -05:00
2dd80eb0f4
C64: Implement more CIA features and CIA/VIA defaults.
2019-07-04 00:31:48 -05:00
32d59e8514
C64: Implement more VIA features.
2019-07-04 00:23:11 -05:00
7fbccb7a46
C64: Use write protection on G64 images (which are often copy protected), and disable it on D64 images.
2019-07-04 00:14:21 -05:00
4e1892d094
C64: Allow writing to disk.
2019-07-04 00:11:03 -05:00
e74dfe15a8
C64: VIA PB7 output timing adjusted to match datasheet.
2019-07-04 00:00:05 -05:00
4e91f88af3
Use nameof in cores
2019-03-28 14:18:58 +11:00
adelikat