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3.0.1-5664-2df3434

AndroidRelease7

Project64-3.0.0-5632-f83bee9

v2.2

v2.3

v2.3.1

v2.3.2

Mono Color

• b92e6bd752 Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT zilmar 2024-04-25 20:22:47 +0930
• d658477cf4 Core: get CX86RecompilerOps::Compile_Branch to clear status flags zilmar 2024-04-18 17:31:19 +0930
• b313640831 Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected zilmar 2024-04-18 17:28:23 +0930
• 1172b6e04d Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly zilmar 2024-04-18 17:21:39 +0930
• 38738b783d Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword zilmar 2024-04-18 17:11:45 +0930
• 7dc53e51cf Core: Get CompileCheckFPUInput to better handle 64bit value check zilmar 2024-04-18 17:00:29 +0930
• a9875b7d61 Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation zilmar 2024-04-18 16:58:18 +0930
• 3203322d8b Core: Get COP1_D_CVT_L to use COP1_S_CVT zilmar 2024-04-18 16:56:30 +0930
• 9e73771815 Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L zilmar 2024-04-18 16:51:53 +0930
• fe87142657 Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation zilmar 2024-04-18 16:42:48 +0930
• 4071b52810 Core: CX86RegInfo::UnMap_X86reg should fail on a protected register zilmar 2024-04-18 16:41:03 +0930
• 79f7aa9927 Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it zilmar 2024-04-18 16:34:49 +0930
• 0cf4c7dc11 Core: get COP1_D_CMP to work in recompiler zilmar 2024-04-11 18:14:44 +0930
• 9272ac05f6 Core: refactor S opcodes to one central function zilmar 2024-04-11 18:09:30 +0930
• e7178dbdec Core: Fix CX86RecompilerOps::COP1_D_CVT_S zilmar 2024-03-28 20:05:27 +1030
• 8bb2445263 Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word zilmar 2024-03-28 20:02:24 +1030
• 560c49ba2d
  Core: Fix N64 disk IPL load address check (#2401) François Berder 2024-03-21 08:22:09 +0100
• 45fb2ad965 Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected zilmar 2024-03-21 17:44:53 +1030
• 2811b63ff0 Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W zilmar 2024-03-21 17:41:29 +1030
• 33d2722841 Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W zilmar 2024-03-21 17:40:14 +1030
• 9a9c2e5439 Core: Update CX86RecompilerOps::COP1_D_CEIL_W zilmar 2024-03-21 17:32:12 +1030
• 401efae0d9 Core: fix up CX86RecompilerOps::COP1_D_ROUND_W zilmar 2024-03-21 17:28:16 +1030
• 772a20f07d Core: Update CX86RecompilerOps::COP1_D_SQRT zilmar 2024-03-21 17:15:10 +1030
• 87c732b65d Core: update CX86RecompilerOps::COP1_D_NEG zilmar 2024-03-21 17:14:00 +1030
• ece5e30a80 Core: create a function to handle .d recompiler opcodes that use fd and fs zilmar 2024-03-21 17:13:16 +1030
• 664fe532f4 Adding functionality to copy a specified number of commands in the Commands window Summate 2024-03-17 22:26:47 -0500
• 5133d47502 Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode zilmar 2024-03-14 18:12:58 +1030
• 6e95cb463b Allowing a paste into a number field to be trimmed automatically Summate 2024-03-10 19:12:17 -0500
• 10b41dfef0
  Update Portuguese translation (#2412) Hugo Carvalho 2024-03-07 10:43:58 +0000
• 98b1bddc64 Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT zilmar 2024-03-07 21:12:57 +1030
• 97ec1f533b Core: Make sure precision is set to 53bit zilmar 2024-03-07 20:52:24 +1030
• 1f322c7efd
  Update Portuguese translation Hugo Carvalho 2024-03-06 13:35:29 +0000
• 290040d945 Merge branch 'develop' of https://github.com/project64/project64 into develop zilmar 2024-02-29 16:07:32 +1030
• 190c408019 Core: Fix clang formatting in x86/x86RecompilerOps.cpp zilmar 2024-02-29 16:06:56 +1030
• 565d45de8a
  Update minimum requirements for Project64 (#2409) Derek "Turtle" Roe 2024-02-28 22:48:28 -0600
• 1bde8589e9
  Cheat (#2410) jeremie-78 2024-02-29 05:47:48 +0100
• f7aa6ef6cb Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions zilmar 2024-02-29 15:16:29 +1030
• 25dc3ed36f Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes zilmar 2024-02-29 15:13:14 +1030
• 021d97e54b
  Update Zelda no Densetsu - Mujura no Kamen - Zelda Collection Version (J) (GC).cht jeremie-78 2024-02-26 12:59:06 +0100
• 2c63bcf079
  Update Zelda no Densetsu - Mujura no Kamen (J) (V1.1).cht jeremie-78 2024-02-26 12:58:23 +0100
• 1955f98ac1
  Update Zelda no Densetsu - Mujura no Kamen (J) (V1.0).cht jeremie-78 2024-02-26 12:57:53 +0100
• 72d25e1eb0
  Update The Legend of Zelda - Majora's Mask - Collector's Edition (U) (GC).cht jeremie-78 2024-02-26 12:56:56 +0100
• 00cb413ae8
  Update The Legend of Zelda - Majora's Mask - Collector's Edition (E) (GC Version).cht jeremie-78 2024-02-26 12:56:22 +0100
• 87f29d1ffe
  Update The Legend of Zelda - Majora's Mask (U).cht jeremie-78 2024-02-26 12:55:30 +0100
• d2f3b5ffb8
  Update The Legend of Zelda - Majora's Mask (E) (M4) (V1.1).cht jeremie-78 2024-02-26 12:53:28 +0100
• 93c11c5ca3
  Update The Legend of Zelda - Majora's Mask (E) (M4) (V1.0).cht jeremie-78 2024-02-26 12:52:45 +0100
• fb098bc233 Change minimum to supported Derek "Turtle" Roe 2024-02-25 15:45:42 -0600
• 981a39705f Merge branch 'develop' of https://github.com/DerekTurtleRoe/project64 into develop Derek "Turtle" Roe 2024-02-25 01:53:16 -0600
• 466a5628e7 Update minimum requirements Derek "Turtle" Roe 2024-02-25 01:53:07 -0600
• d2649f7a13 Core: Some clean up recompiler ops zilmar 2024-02-22 19:56:23 +1030
• fae0b81e21 Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register zilmar 2024-02-22 19:41:10 +1030
• e082cd55df Core: Get COP1_D_TRUNC_W to work in recompiler zilmar 2024-02-15 21:08:49 +1030
• 2559d23592 Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID zilmar 2024-02-15 21:02:27 +1030
• 46f6fae40f Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit zilmar 2024-02-15 21:00:12 +1030
• 2014237ed6 Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler zilmar 2024-02-08 19:34:14 +1030
• ad1a2a2d9a Core: Update neg.s for the recompiler zilmar 2024-02-01 18:17:03 +1030
• b6671adf5d Core: Update abs.s for recompiler zilmar 2024-02-01 18:15:33 +1030
• bc3fe0fe16 Core: Handle FP Status Reg being mapped better zilmar 2024-01-25 18:46:39 +1030
• 7707f9c7b2 Core: Fix up mov.s and mov.d for correct behaviour in the recompiler zilmar 2024-01-25 16:25:06 +1030
• 272144dc37 Core: check timer on cop1 unusable zilmar 2024-01-25 16:23:03 +1030
• f0f44c67f4 Core: Make mov.s the same as mov.d zilmar 2024-01-25 15:32:56 +1030
• 7ed94b653e Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions zilmar 2024-01-18 17:09:27 +1030
• 2231e8d6c0 Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64 zilmar 2024-01-18 16:53:14 +1030
• 71067ccdc4 Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP zilmar 2024-01-11 18:17:05 +1030
• 5c56f9df83 RSP: Update the size of the skip in the length for DMA zilmar 2024-01-11 17:50:23 +1030
• 4dc3e35bb4 Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions zilmar 2024-01-04 16:51:11 +1030
• f8089f565e Core: Unmap FPU_Float with writing to m_FPR_UDW zilmar 2024-01-04 14:40:42 +1030
• 552b8f744a Core: update Format_Name to match FPU_STATE zilmar 2024-01-04 13:11:21 +1030
• 6ca8333d39 Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions zilmar 2024-01-04 12:39:51 +1030
• c9d2bbd221 Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped zilmar 2024-01-04 12:37:06 +1030
• 0998f0ff0e Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer zilmar 2024-01-04 12:32:55 +1030
• 23cff4d7c5 Core: Add x86 asm opcode Jnp zilmar 2024-01-04 12:31:26 +1030
• 91a8a828d7 Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW zilmar 2024-01-04 12:01:21 +1030
• 320769d991 Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr zilmar 2024-01-04 10:33:07 +1030
• dafa1fb24d Core: Have COP1_W_CVT_S handle the initialization of exceptions zilmar 2023-12-28 11:19:06 +1030
• 17288c90c0 Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32 zilmar 2023-12-28 10:23:18 +1030
• e2306e3541 Core: Get COP1_S_CVT_W to handle inexact zilmar 2023-12-28 09:21:53 +1030
• 1effbe126f
  Update UIResources.rc Jayden Enma 2023-12-22 20:17:24 -0600
• 1a38f99c16
  Delete Source/Project64/UserInterface/SupportWindow.h Jayden Enma 2023-12-22 20:15:21 -0600
• 0317abf408
  Delete Source/Project64/UserInterface/SupportWindow.cpp Jayden Enma 2023-12-22 20:15:12 -0600
• a7f969b4c7
  Delete Source/Project64/UserInterface/SupportEnterCode.h Jayden Enma 2023-12-22 20:14:15 -0600
• 0d419f4a5d
  Delete Source/Project64/UserInterface/SupportEnterCode.cpp Jayden Enma 2023-12-22 20:14:07 -0600
• ad89bf1e23
  Delete Source/Project64/UserInterface/ProjectSupport.h Jayden Enma 2023-12-22 20:13:57 -0600
• dea58c8581
  Delete Source/Project64/UserInterface/ProjectSupport.cpp Jayden Enma 2023-12-22 20:13:46 -0600
• 8399fdb893 Core: Clear the Divide-by-zero flag zilmar 2023-12-21 21:24:33 +1030
• d14a639a62 Core: Implement COP1_S_DIV with fpu exceptions zilmar 2023-12-21 14:11:29 +1030
• 8e54ec8c8e Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis zilmar 2023-12-21 14:10:21 +1030
• b263ee10b0 Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0 zilmar 2023-12-21 10:41:16 +1030
• 1810bfda5c Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops zilmar 2023-12-21 10:38:49 +1030
• 2c1610cfe2 Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode zilmar 2023-12-21 10:37:27 +1030
• 6610ae3058 Core: Have R4300iInstruction in CRecompilerOpsBase zilmar 2023-12-21 10:34:03 +1030
• 8e3fb3e302 Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference zilmar 2023-12-21 10:26:10 +1030
• c8e73ba18e Core: Handle unaligned SW exception in the recompiler zilmar 2023-12-14 23:04:26 +1030
• 972943cff7 Core: Allow LW to R0 be able to generate an exception zilmar 2023-12-14 17:21:52 +1030
• 89a6eaf9d1 Core: Add RecordLLAddress for 32bit register pointer zilmar 2023-12-14 13:52:15 +1030
• 67f5e4f854 Core: in LL for recompiler handle storing the address in COP[17] zilmar 2023-12-14 13:10:20 +1030
• d5a5f4cdac Core: Have Store Instruc rdb and user rdb matching zilmar 2023-12-14 12:21:03 +1030
• 5fec3f8d31 Core: remove the global of g_TLB zilmar 2023-12-14 12:09:24 +1030
• c67f3f0e97 Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it zilmar 2023-12-14 11:18:07 +1030
• cf236d3329 Core: Fix N64 disk IPL load address check Francois Berder 2023-12-10 13:36:44 +0100