zilmar
|
fdc637516f
|
Core: remove Double_RoundToInteger64
|
2023-05-09 13:05:58 +09:30 |
|
zilmar
|
5a23f48629
|
Core: remove Double_RoundToInteger32
|
2023-05-09 12:57:08 +09:30 |
|
zilmar
|
e5b1a9469a
|
Core: remove Float_RoundToInteger64
|
2023-05-09 12:50:23 +09:30 |
|
zilmar
|
2c19c2c362
|
Core: Handle CPO1 unimplemented op
|
2023-05-09 11:28:59 +09:30 |
|
zilmar
|
85f4f147a1
|
Core: Remove Float_RoundToInteger32
|
2023-05-09 09:40:10 +09:30 |
|
zilmar
|
49a385e743
|
Core: Split CheckFPUException into CheckFPUException and CheckFPUInvalidException
|
2023-05-09 08:06:15 +09:30 |
|
zilmar
|
5cfb80fcfc
|
Core: Improve R4300iOp::COP1_S_CVT_W
|
2023-04-24 19:02:00 +09:30 |
|
zilmar
|
71ef28fd55
|
Core: Add R4300iOp::COP1_W_CVT_W
|
2023-04-24 18:55:06 +09:30 |
|
zilmar
|
ab8b004b71
|
Core: Add a setting for fpu reg caching
|
2023-04-17 18:47:33 +09:30 |
|
zilmar
|
cba01b2063
|
Core: Improve R4300iOp::COP1_L_CVT_D
|
2023-04-17 18:08:51 +09:30 |
|
zilmar
|
d9e69fee65
|
Core: Improve R4300iOp::COP1_D_CMP
|
2023-04-17 18:07:58 +09:30 |
|
zilmar
|
0cc6d21ad1
|
Core: Improve R4300iOp::COP1_S_CMP
|
2023-04-17 18:06:42 +09:30 |
|
zilmar
|
9297b1c4b8
|
Core: Improve COP1_S_CVT_D, COP1_W_CVT_D, COP1_D_CVT_S, COP1_W_CVT_S, COP1_L_CVT_S,
|
2023-04-11 16:20:24 +09:30 |
|
zilmar
|
9a04293a67
|
Update arm/arm64 to use asmjit
|
2023-04-05 10:16:21 +09:30 |
|
zilmar
|
2c40d47a34
|
Start to look at x64 recompiler
|
2023-04-04 17:44:42 +09:30 |
|
zilmar
|
422a42cae3
|
Core: More work improve the accuracy of cop1
|
2023-03-28 13:12:59 +10:30 |
|
zilmar
|
ce69324dbe
|
Core: Update R4300iOp::COP1_S_MUL to handle exceptions
|
2023-03-21 10:49:49 +10:30 |
|
zilmar
|
cbf67cede4
|
Core: Update sub.d to handle exceptions
|
2023-03-20 17:17:31 +10:30 |
|
zilmar
|
9093b42d47
|
Core: improve the accuracy of COP1_S_SUB
|
2023-03-06 20:58:47 +10:30 |
|
zilmar
|
306f21b5fa
|
Core: Improve accuracy of add.d
|
2023-03-06 18:28:32 +10:30 |
|
zilmar
|
1864adcb35
|
Core: improve the accuracy of COP1_S_ADD
|
2023-02-21 14:54:22 +10:30 |
|
zilmar
|
3acd56ae61
|
Core Fix up clang formatting
|
2023-02-14 08:05:40 +10:30 |
|
zilmar
|
e14e10f4b0
|
Core: Fix handling of R4300iOp::COP1_S_CMP and R4300iOp::COP1_D_CMP
|
2023-02-13 16:22:50 +10:30 |
|
zilmar
|
a8a553b316
|
Core: fix code to make clang happy
|
2023-01-31 07:54:47 +10:30 |
|
zilmar
|
83a7d9e3f2
|
Core: Start to improve the accuracy of R4300iOp::COP1_S_ADD
|
2023-01-30 20:36:58 +10:30 |
|
zilmar
|
7affd514c0
|
Core: Convert TEST_COP1_USABLE_EXCEPTION from a macro to a function
|
2023-01-30 11:40:03 +10:30 |
|
zilmar
|
f802b18cdc
|
Core: Change to using fenv.h instead of including the code directly
|
2023-01-30 10:07:51 +10:30 |
|
zilmar
|
80aecdc5e3
|
Core: Improve R4300iOp::COP1_CT
|
2023-01-02 19:49:19 +10:30 |
|
zilmar
|
cbacddb65e
|
Core: Make 32bit CPU recompiler only setting
|
2022-12-19 09:07:26 +10:30 |
|
zilmar
|
6c154f6547
|
Core: Add Cop2/Cop3 handling exception
|
2022-12-12 21:29:16 +10:30 |
|
zilmar
|
c8bb04b6b0
|
Core: Mask COP1_CT reg 31
|
2022-12-12 19:04:03 +10:30 |
|
zilmar
|
b3c6858b69
|
Core: Change COP0 registers to use an enum
|
2022-11-07 09:24:58 +10:30 |
|
zilmar
|
fd71b2dfcb
|
Core: Handle branch/jump in a delay slot in the Interpreter
|
2022-11-01 08:59:15 +10:30 |
|
zilmar
|
65bbc375b9
|
Core: Fix R4300iOp::LWC1 to have 64bit address
|
2022-10-17 08:36:17 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
179282043f
|
Project64: Code cleanup
|
2022-09-26 12:01:54 +09:30 |
|
zilmar
|
a2981ff4d8
|
Core: Make Load/Store use 64bit vaddr
|
2022-09-19 21:36:36 +09:30 |
|
zilmar
|
1c77f6f0fd
|
Core: Make Cop0 64bit
|
2022-09-19 16:36:44 +09:30 |
|
zilmar
|
05d46c9487
|
Core: Handle reserve instruction 31
|
2022-09-19 12:12:08 +09:30 |
|
zilmar
|
524f56eda7
|
Core: fix srav in the interpter
|
2022-09-05 17:42:15 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
52a30b78fb
|
Core: Handle div/0 better
|
2022-08-22 22:13:53 +09:30 |
|
zilmar
|
71ddfd885d
|
Core: Add BGEZALL to interrupter
|
2022-08-15 10:18:51 +09:30 |
|
zilmar
|
e724595ac2
|
Core: Add DADDI
|
2022-08-15 10:05:16 +09:30 |
|
zilmar
|
5ea06d958e
|
Core: have SB/SH be able to write to rom handler
|
2022-08-08 19:33:16 +09:30 |
|
zilmar
|
0419ba232e
|
Core: Add option to step code at break opcode
|
2022-08-01 11:43:17 +09:30 |
|
zilmar
|
b987a1693c
|
Core: Do not end emulation by default on perm loop
|
2022-08-01 10:59:16 +09:30 |
|
zilmar
|
d6a217ca86
|
Core: fix issue with R4300iOp::SPECIAL_SRA
|
2022-08-01 10:03:06 +09:30 |
|
zilmar
|
09b535551d
|
Core: Move DelaySlotEffectsCompare into R4300iInstruction
|
2022-07-25 16:35:42 +09:30 |
|
zilmar
|
c3cae358a1
|
Core: Open debugger on unknown opcode
|
2022-07-25 14:07:12 +09:30 |
|
zilmar
|
f62f8207ec
|
Core: Initiate PREVID
|
2022-07-18 18:56:52 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
86aa483a38
|
Core: Move memory exceptions out of interrupter ops and in to Memory Manager
|
2022-06-13 11:24:36 +09:30 |
|
zilmar
|
603ed853bc
|
Core: Some code clean up for load/store non memory
|
2022-05-30 20:20:25 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
5a49331c0b
|
Core: Direct tlb method to read and write to memory
|
2022-05-02 20:22:31 +09:30 |
|
zilmar
|
b74a2dc69f
|
[Core] Change TranslateVaddr to VAddrToPAddr
|
2022-05-02 07:36:50 +09:30 |
|
zilmar
|
7fd239cf82
|
Core: Change NextInstruction to PipelineStage
|
2022-01-18 18:17:21 +10:30 |
|
zilmar
|
30a40ea0a8
|
Core: Remove the option to turn off tlb
|
2022-01-10 17:46:01 +10:30 |
|
zilmar
|
40683ecf79
|
Core: Remove legacy code
|
2022-01-05 08:59:12 +10:30 |
|
zilmar
|
7e80d952cb
|
Project64-core: General Code clean up
|
2022-01-04 10:26:14 +10:30 |
|
zilmar
|
ee864797ab
|
vgturtle127's Beautification 14 - Source\Project64-video directory and final cleanup
|
2021-05-18 21:21:36 +09:30 |
|
zilmar
|
c512a592a7
|
Move class out of file names
|
2021-04-14 15:04:15 +09:30 |
|
zilmar
|
662637460e
|
Remove Disable copy constructor comments
|
2021-04-13 09:37:11 +09:30 |
|
zilmar
|
cf58754414
|
Change NULL to nullptr
|
2021-04-12 21:05:39 +09:30 |
|
zilmar
|
5c60ea213f
|
Update copyright date
|
2021-03-02 12:43:17 +10:30 |
|
zilmar
|
cd16a8cc48
|
Clean up some warnings
|
2021-01-19 16:28:59 +10:30 |
|
zilmar
|
185c6586b4
|
Project64: Add TLB_WRITE_EXCEPTION
|
2020-03-04 10:33:18 +10:30 |
|
KrimtonZ
|
0baf3ef263
|
Fix Trap Interpreter Functions, add recompiler trap functions
|
2019-12-17 09:08:15 -06:00 |
|
KrimtonZ
|
0e5c771408
|
remove HaveDebugger requirement, remove redundant code
|
2019-12-16 14:59:40 -06:00 |
|
KrimtonZ
|
b9be612ac5
|
add remaining trap instructions, properly implement traps for the interpreter core
|
2019-12-16 14:15:26 -06:00 |
|
oddMLan
|
01d4ed0bc3
|
Change some error message boxes to warnings
|
2019-04-15 08:58:22 -07:00 |
|
shygoo
|
6b34e8f77c
|
[Debugger] Add CPU exception breakpoint window
|
2019-01-17 03:34:24 -06:00 |
|
shygoo
|
4d322191c2
|
[Debugger] Add CPU Log, break and show log/commands window on CPU errors
|
2019-01-14 03:18:43 -06:00 |
|
shygoo
|
77daf1bad4
|
[Debugger] Add memory locks feature (interpreter)
|
2018-03-17 20:14:52 -05:00 |
|
zilmar
|
e1c464e309
|
[Debugger] If stepping ops already, ignore finding a memory BreakPoint
|
2018-03-02 18:23:47 +11:00 |
|
zilmar
|
9729fad9da
|
[Debugger] Add store breakpoints to recompiler
|
2018-02-13 18:16:53 +11:00 |
|
zilmar
|
622d5d5d3f
|
[Debugger] Fix Read break points
|
2018-02-05 17:43:46 +11:00 |
|
zilmar
|
076280b9ba
|
[Debugger] Add unaligned write breakpoints
|
2018-02-02 04:28:08 +11:00 |
|
zilmar
|
3d7e9b40b0
|
[Debugger] Make skip a setting
|
2018-01-17 22:36:28 +11:00 |
|
zilmar
|
8a85f1e6a4
|
[Debugger] Make waiting for step a setting
|
2018-01-17 08:26:54 +11:00 |
|
zilmar
|
7e1e7bf39b
|
[Debugger] Change bHaveDebugger to HaveDebugger
|
2018-01-16 08:23:21 +11:00 |
|
zilmar
|
4b7fafbded
|
Make sure R0 is 0 in Interpreter
|
2018-01-03 19:16:01 +11:00 |
|
zilmar
|
857f87116e
|
[Project64] Change g_Settings->LoadBool(Debugger_Enabled) to CDebugSettings::bHaveDebugger()
|
2017-09-13 20:08:47 +10:00 |
|
zilmar
|
10f662da94
|
[Project64] Better handling of div / 0
|
2017-08-31 09:43:58 +10:00 |
|
shygoo
|
e64a6c5965
|
Debugger: Add stack trace window
|
2017-08-29 23:54:06 -05:00 |
|
zilmar
|
a61a466776
|
[Project64] Fix up some changes to debugger commit
|
2017-08-21 08:48:31 +10:00 |
|
shygoo
|
47fd0632ff
|
Add debug features
|
2017-08-18 00:08:22 -05:00 |
|
zilmar
|
c3d89e8fc1
|
[Project64] Fix Round 0.5 in interpter
|
2017-04-24 07:36:40 +10:00 |
|
zilmar
|
42084371b7
|
[Project64] Get COP1_D_ROUND_L to use _FPR_D
|
2017-04-24 07:33:35 +10:00 |
|
zilmar
|
b4fa83e0ad
|
[Project64] Clean up eol blank space InterpreterOps.cpp
|
2017-04-24 07:30:49 +10:00 |
|
zilmar
|
812dae99f5
|
[Project64] Fix bug in Double_RoundToInteger32 for arm
|
2016-09-24 08:36:14 +10:00 |
|
zilmar
|
4c0b8d154e
|
[Project64] Remove DSRL32 and DSRA32 from 32bit interpter
|
2016-08-12 23:47:35 +10:00 |
|
zilmar
|
7e0dd2e83b
|
[Project64] Some code cleanup in InterpreterCPU.cpp
|
2016-08-07 16:18:34 +10:00 |
|
zilmar
|
433c76446b
|
[Project64] Move more x86 code in to x86/x86RecompilerOps.cpp
|
2016-07-03 15:22:14 +10:00 |
|
zilmar
|
c8cd2914a6
|
{project64] Move compiling load/store instructions in to x86/x86RecompilerOps.cpp
|
2016-06-29 23:40:36 +10:00 |
|
LegendOfDragoon
|
32ade84138
|
Implement COP1_D_ROUND_L in cpu interpreter
|
2016-05-22 23:37:45 -07:00 |
|
LegendOfDragoon
|
b2b10969c9
|
Implement COP1_S_ROUND_L in cpu interpreter
|
2016-05-22 23:20:49 -07:00 |
|
zilmar
|
b55cc5f78e
|
[Project64] fix up so trunc is in for Visual Studio 2012
|
2016-04-18 17:20:12 +10:00 |
|
Nicholas
|
1ed5b044b3
|
[Project64] fix issue in 2012
|
2016-02-24 10:06:52 +11:00 |