zilmar
|
d9e69fee65
|
Core: Improve R4300iOp::COP1_D_CMP
|
2023-04-17 18:07:58 +09:30 |
|
zilmar
|
0cc6d21ad1
|
Core: Improve R4300iOp::COP1_S_CMP
|
2023-04-17 18:06:42 +09:30 |
|
zilmar
|
9297b1c4b8
|
Core: Improve COP1_S_CVT_D, COP1_W_CVT_D, COP1_D_CVT_S, COP1_W_CVT_S, COP1_L_CVT_S,
|
2023-04-11 16:20:24 +09:30 |
|
zilmar
|
9a04293a67
|
Update arm/arm64 to use asmjit
|
2023-04-05 10:16:21 +09:30 |
|
zilmar
|
2c40d47a34
|
Start to look at x64 recompiler
|
2023-04-04 17:44:42 +09:30 |
|
zilmar
|
422a42cae3
|
Core: More work improve the accuracy of cop1
|
2023-03-28 13:12:59 +10:30 |
|
zilmar
|
ce69324dbe
|
Core: Update R4300iOp::COP1_S_MUL to handle exceptions
|
2023-03-21 10:49:49 +10:30 |
|
zilmar
|
cbf67cede4
|
Core: Update sub.d to handle exceptions
|
2023-03-20 17:17:31 +10:30 |
|
zilmar
|
9093b42d47
|
Core: improve the accuracy of COP1_S_SUB
|
2023-03-06 20:58:47 +10:30 |
|
zilmar
|
306f21b5fa
|
Core: Improve accuracy of add.d
|
2023-03-06 18:28:32 +10:30 |
|
zilmar
|
1864adcb35
|
Core: improve the accuracy of COP1_S_ADD
|
2023-02-21 14:54:22 +10:30 |
|
zilmar
|
3acd56ae61
|
Core Fix up clang formatting
|
2023-02-14 08:05:40 +10:30 |
|
zilmar
|
e14e10f4b0
|
Core: Fix handling of R4300iOp::COP1_S_CMP and R4300iOp::COP1_D_CMP
|
2023-02-13 16:22:50 +10:30 |
|
zilmar
|
a8a553b316
|
Core: fix code to make clang happy
|
2023-01-31 07:54:47 +10:30 |
|
zilmar
|
83a7d9e3f2
|
Core: Start to improve the accuracy of R4300iOp::COP1_S_ADD
|
2023-01-30 20:36:58 +10:30 |
|
zilmar
|
7affd514c0
|
Core: Convert TEST_COP1_USABLE_EXCEPTION from a macro to a function
|
2023-01-30 11:40:03 +10:30 |
|
zilmar
|
f802b18cdc
|
Core: Change to using fenv.h instead of including the code directly
|
2023-01-30 10:07:51 +10:30 |
|
zilmar
|
80aecdc5e3
|
Core: Improve R4300iOp::COP1_CT
|
2023-01-02 19:49:19 +10:30 |
|
zilmar
|
cbacddb65e
|
Core: Make 32bit CPU recompiler only setting
|
2022-12-19 09:07:26 +10:30 |
|
zilmar
|
6c154f6547
|
Core: Add Cop2/Cop3 handling exception
|
2022-12-12 21:29:16 +10:30 |
|
zilmar
|
c8bb04b6b0
|
Core: Mask COP1_CT reg 31
|
2022-12-12 19:04:03 +10:30 |
|
zilmar
|
b3c6858b69
|
Core: Change COP0 registers to use an enum
|
2022-11-07 09:24:58 +10:30 |
|
zilmar
|
fd71b2dfcb
|
Core: Handle branch/jump in a delay slot in the Interpreter
|
2022-11-01 08:59:15 +10:30 |
|
zilmar
|
65bbc375b9
|
Core: Fix R4300iOp::LWC1 to have 64bit address
|
2022-10-17 08:36:17 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
179282043f
|
Project64: Code cleanup
|
2022-09-26 12:01:54 +09:30 |
|
zilmar
|
a2981ff4d8
|
Core: Make Load/Store use 64bit vaddr
|
2022-09-19 21:36:36 +09:30 |
|
zilmar
|
1c77f6f0fd
|
Core: Make Cop0 64bit
|
2022-09-19 16:36:44 +09:30 |
|
zilmar
|
05d46c9487
|
Core: Handle reserve instruction 31
|
2022-09-19 12:12:08 +09:30 |
|
zilmar
|
524f56eda7
|
Core: fix srav in the interpter
|
2022-09-05 17:42:15 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
52a30b78fb
|
Core: Handle div/0 better
|
2022-08-22 22:13:53 +09:30 |
|
zilmar
|
71ddfd885d
|
Core: Add BGEZALL to interrupter
|
2022-08-15 10:18:51 +09:30 |
|
zilmar
|
e724595ac2
|
Core: Add DADDI
|
2022-08-15 10:05:16 +09:30 |
|
zilmar
|
5ea06d958e
|
Core: have SB/SH be able to write to rom handler
|
2022-08-08 19:33:16 +09:30 |
|
zilmar
|
0419ba232e
|
Core: Add option to step code at break opcode
|
2022-08-01 11:43:17 +09:30 |
|
zilmar
|
b987a1693c
|
Core: Do not end emulation by default on perm loop
|
2022-08-01 10:59:16 +09:30 |
|
zilmar
|
d6a217ca86
|
Core: fix issue with R4300iOp::SPECIAL_SRA
|
2022-08-01 10:03:06 +09:30 |
|
zilmar
|
09b535551d
|
Core: Move DelaySlotEffectsCompare into R4300iInstruction
|
2022-07-25 16:35:42 +09:30 |
|
zilmar
|
c3cae358a1
|
Core: Open debugger on unknown opcode
|
2022-07-25 14:07:12 +09:30 |
|
zilmar
|
f62f8207ec
|
Core: Initiate PREVID
|
2022-07-18 18:56:52 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
86aa483a38
|
Core: Move memory exceptions out of interrupter ops and in to Memory Manager
|
2022-06-13 11:24:36 +09:30 |
|
zilmar
|
603ed853bc
|
Core: Some code clean up for load/store non memory
|
2022-05-30 20:20:25 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
5a49331c0b
|
Core: Direct tlb method to read and write to memory
|
2022-05-02 20:22:31 +09:30 |
|
zilmar
|
b74a2dc69f
|
[Core] Change TranslateVaddr to VAddrToPAddr
|
2022-05-02 07:36:50 +09:30 |
|
zilmar
|
7fd239cf82
|
Core: Change NextInstruction to PipelineStage
|
2022-01-18 18:17:21 +10:30 |
|
zilmar
|
30a40ea0a8
|
Core: Remove the option to turn off tlb
|
2022-01-10 17:46:01 +10:30 |
|
zilmar
|
40683ecf79
|
Core: Remove legacy code
|
2022-01-05 08:59:12 +10:30 |