zilmar
|
5c65bebe9e
|
RSP: Update VAdd code (SQV/LQV order changed as well)
|
2023-07-21 07:25:17 +09:30 |
|
zilmar
|
2cf740565e
|
RSP: Add dummy vsut
|
2023-07-20 09:40:42 +09:30 |
|
zilmar
|
e88e827d64
|
RSP Add dummy LWV
|
2023-07-20 08:59:36 +09:30 |
|
zilmar
|
cf7628cc1d
|
RSP: Update RSP_LRV_DMEM
|
2023-07-18 10:05:25 +09:30 |
|
zilmar
|
4265bdfb43
|
RSP: Add lwu
|
2023-07-18 10:04:54 +09:30 |
|
zilmar
|
bd357c65b0
|
RSP: fix vmov
|
2023-07-18 09:56:31 +09:30 |
|
zilmar
|
6e03d6ad7b
|
RSP: Add method to get element specifier index from the Vector
|
2023-07-18 07:55:06 +09:30 |
|
zilmar
|
97fccb1c36
|
RSP: Change EleSpec to be 16 and use .e instead of rs
|
2023-07-18 07:36:25 +09:30 |
|
zilmar
|
97fbbffee8
|
RSP: A little clean up of VABS
|
2023-07-18 07:27:49 +09:30 |
|
zilmar
|
ee452143ff
|
RSP: Change the name of the opcode that register ops use
|
2023-07-18 07:22:27 +09:30 |
|
zilmar
|
b7d7884e22
|
RSP: Make a class for the RSP Vector
|
2023-07-13 21:09:18 +09:30 |
|
zilmar
|
353ef5ed89
|
RSP: When command window is entered, always step commands
|
2023-07-06 20:56:00 +09:30 |
|
zilmar
|
115881524b
|
RSP: Better handling on unaligned SH and SW
|
2023-07-06 20:55:02 +09:30 |
|
zilmar
|
fbb388fa0f
|
Rsp: Fix capitalization in rsp_UnknownOpcode
|
2023-07-06 20:51:17 +09:30 |
|
zilmar
|
07cf94bde3
|
RSP: only look at SP_STATUS_HALT when seeing if the RSP should run
|
2023-07-06 20:49:14 +09:30 |
|
zilmar
|
7dc30b1d6d
|
RSP: Update dissam of load/store vector ops
|
2023-07-06 17:49:15 +09:30 |
|
zilmar
|
f8f9688386
|
RSP: get RSP_LH_DMEM and RSP_LW_DMEM to handle end of memory roll over
|
2023-06-29 14:52:46 +09:30 |
|
zilmar
|
cfc63532dd
|
RSP: move p_func from RspTypes.h to Cpu.h
|
2023-06-29 12:31:25 +09:30 |
|
zilmar
|
02da0ccad1
|
RSP: Use bool instead of Boolean
|
2023-06-29 12:29:07 +09:30 |
|
zilmar
|
2ce9eaa667
|
RSP: Rename Types.h to RspTypes.h
|
2023-06-29 11:03:55 +09:30 |
|
zilmar
|
1c61f15ea9
|
RSP: Update display of vector ops
|
2023-06-29 10:59:54 +09:30 |
|
zilmar
|
080a3b69ac
|
RSP: Create a RSP instruction for decoding the RSP op
|
2023-06-15 21:09:44 +09:30 |
|
zilmar
|
df215c1cc5
|
RSP: Fix up rename of filters file
|
2023-06-15 14:48:07 +09:30 |
|
zilmar
|
ef24ec11d8
|
Rename RSP to Project64-rsp
|
2023-06-15 14:45:27 +09:30 |
|
zilmar
|
187bd64915
|
Core: Update how exceptions are handled with the recompiler
|
2023-06-08 16:25:05 +09:30 |
|
Nayla
|
18a712ce6a
|
Update Interface.cpp (#2367)
|
2023-06-03 07:11:57 +09:30 |
|
zilmar
|
f4459fe143
|
RSP: Update RSP name in package_zip.cmd
|
2023-06-02 10:52:10 +09:30 |
|
zilmar
|
98b96a60cb
|
RSP: Get the code to conform to clang-format
|
2023-06-01 21:16:23 +09:30 |
|
zilmar
|
90fefed579
|
RSP: Fix text when adding tab to registers
|
2023-06-01 19:40:53 +09:30 |
|
zilmar
|
1522f17b9c
|
RSP: Convert base code to be compiled as c++ instead of C
|
2023-06-01 17:11:26 +09:30 |
|
zilmar
|
a39ebe7d37
|
Core: Create InitFpuOperation
|
2023-05-27 10:01:19 +09:30 |
|
zilmar
|
e2eebe566d
|
Core: fix up for clang
|
2023-05-18 18:05:54 +09:30 |
|
zilmar
|
b438fddf2e
|
Core: Add CP2 handling
|
2023-05-18 18:04:41 +09:30 |
|
zilmar
|
3b8dfce64a
|
Core: Convert DoBreakException to TriggerException
|
2023-05-18 11:47:00 +09:30 |
|
zilmar
|
b2c2a03a2e
|
Core: convert DoFloatingPointException to TriggerException
|
2023-05-18 11:41:20 +09:30 |
|
zilmar
|
0dfab78c88
|
Core: Convert DoCopUnusableException to TriggerException
|
2023-05-18 11:26:36 +09:30 |
|
zilmar
|
456f25eb6b
|
Core: Get DoIntrException to use TriggerException
|
2023-05-18 11:19:26 +09:30 |
|
zilmar
|
252f629e14
|
Core: Convert DoIllegalInstructionException to TriggerException
|
2023-05-18 11:13:22 +09:30 |
|
zilmar
|
59a1277bed
|
Core: Convert GenerateOverflowException to TriggerException
|
2023-05-18 11:05:27 +09:30 |
|
zilmar
|
69fd74ba56
|
Core: Convert DoSysCallException to TriggerException
|
2023-05-18 10:56:06 +09:30 |
|
zilmar
|
17df17805d
|
Core: convert DoTrapException to TriggerException
|
2023-05-18 10:49:58 +09:30 |
|
zilmar
|
74912ca8c2
|
Core: handle jump to unaligned addresses
|
2023-05-18 10:33:57 +09:30 |
|
zilmar
|
6e58edb076
|
Core: Merge CheckFPUException into CheckFPUResult32
|
2023-05-15 23:16:54 +09:30 |
|
zilmar
|
62b29622ca
|
Core: remove usage of fpclassify in CheckFPUInput32 and CheckFPUResult32
|
2023-05-15 22:57:13 +09:30 |
|
zilmar
|
0ddeb6b981
|
Core: remove exception out of R4300iOp::CheckFPUInput32
|
2023-05-15 20:56:56 +09:30 |
|
zilmar
|
fdc637516f
|
Core: remove Double_RoundToInteger64
|
2023-05-09 13:05:58 +09:30 |
|
zilmar
|
5a23f48629
|
Core: remove Double_RoundToInteger32
|
2023-05-09 12:57:08 +09:30 |
|
zilmar
|
e5b1a9469a
|
Core: remove Float_RoundToInteger64
|
2023-05-09 12:50:23 +09:30 |
|
zilmar
|
2c19c2c362
|
Core: Handle CPO1 unimplemented op
|
2023-05-09 11:28:59 +09:30 |
|
zilmar
|
85f4f147a1
|
Core: Remove Float_RoundToInteger32
|
2023-05-09 09:40:10 +09:30 |