zilmar
|
97b2579b4b
|
Core: Have the recompiler just deal with the Program Counter as 32bit
|
2024-11-07 17:05:16 +10:30 |
|
zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
|
2024-06-06 14:09:12 +09:30 |
|
zilmar
|
6610ae3058
|
Core: Have R4300iInstruction in CRecompilerOpsBase
|
2023-12-21 10:34:03 +10:30 |
|
zilmar
|
8e3fb3e302
|
Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference
|
2023-12-21 10:26:10 +10:30 |
|
zilmar
|
c02858c7a0
|
Core: Add LLD opcode
|
2023-09-14 16:31:37 +09:30 |
|
zilmar
|
b438fddf2e
|
Core: Add CP2 handling
|
2023-05-18 18:04:41 +09:30 |
|
zilmar
|
c0341bb759
|
Core: Code clean up for clang
|
2022-12-19 15:35:17 +10:30 |
|
zilmar
|
6c154f6547
|
Core: Add Cop2/Cop3 handling exception
|
2022-12-12 21:29:16 +10:30 |
|
zilmar
|
d35d2e6abe
|
Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction
|
2022-12-05 12:23:09 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
05d46c9487
|
Core: Handle reserve instruction 31
|
2022-09-19 12:12:08 +09:30 |
|
zilmar
|
4218cbad23
|
Core: R4300iInstruction::DecodeSpecialName - Fix up SLL param
|
2022-08-29 08:27:47 +09:30 |
|
zilmar
|
d37d0dc7a5
|
Core: Dissasm of DMFC0 was showing the wrong reg
|
2022-08-01 10:02:07 +09:30 |
|
zilmar
|
09b535551d
|
Core: Move DelaySlotEffectsCompare into R4300iInstruction
|
2022-07-25 16:35:42 +09:30 |
|
zilmar
|
0abc7ccaa4
|
Core: Move OpHasDelaySlot into R4300iInstruction
|
2022-07-25 14:23:12 +09:30 |
|
zilmar
|
1a8a4dd50f
|
Core: Fix some bugs added to R4300iInstruction Param
|
2022-07-25 11:57:19 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |