dcf3f295f1
Make DelaySI Configurable and add/update RDB defaults for the games that will benefit ( #2494 )
...
* Make DelaySI Configurable
make EOF consistent
language update, make control spacing consistent
* update all languages to add semicolon
* Update RDB Info.txt
* Correct manifest wanings
2025-08-07 16:05:57 +09:30
7d5c867bfd
Core: Fixed recompiler memory overrun for m_TestTimer ( #2480 )
2025-05-29 15:43:40 +09:30
4e18341f5f
Input: Use settings to handle emulation pause
2025-05-22 12:25:37 +09:30
1edb5debdf
Core: have CRecompiler::RecompilerMain_VirtualTable handle PC as 32bit and clean up recompiler memory reset
2025-02-27 20:47:37 +10:30
70c44965b0
CIC improvements ( #2455 )
...
* Add CIC CRCs for iQue Player games
* Give proper name to 64DD IPL US CIC
2025-02-21 12:13:52 +10:30
daa8dbc833
core: reset m_InstructionRegion on R4300iOp::ExecuteOps
2025-02-21 12:00:41 +10:30
7eaf1c4ba3
Core: do not write back rt in CX86RecompilerOps::CompileLoadMemoryValue on exception
2025-02-21 11:13:54 +10:30
5d21bf80b9
core: fix up missing exception check in CX86RecompilerOps::SPECIAL_DIV
2025-02-21 06:15:07 +10:30
fa57ce7fb8
core: make CX86RecompilerOps::SPECIAL_JALR handle 64bit PC
2025-02-20 13:25:44 +10:30
5e029ecf6a
Core: CX86RecompilerOps::CompileLoadMemoryValue some work on it generating an exception from invalid load address
2025-02-13 22:20:00 +10:30
bd38e7f2d6
Core: In CX86RecompilerOps::SPECIAL_JR store PC as 64bit
2025-02-13 22:15:20 +10:30
9d28d9cf28
core: More work in making sure the Compiler sets 64bit PC
2025-02-13 16:29:25 +10:30
1debcd1ca5
Core: In CX86RecompilerOps::CompileExit, make sure writing 64bit PC
2025-02-13 16:08:11 +10:30
a82c11b8bb
Core: When syncing CPU make sure PC matches on 64bit address
2025-02-13 15:57:53 +10:30
20f3e5e123
Core: In CX86RecompilerOps::COP1_S_CVT, CX86RecompilerOps::CompileCheckFPUResult32 set softfloat_exceptionFlags to the FPU exception value
2025-02-13 15:55:16 +10:30
a07f6eaf90
Core: In CX86RecompilerOps::COP0_MT update the count register when writing to Count
2025-02-13 12:24:20 +10:30
a5a2c8cf6d
Core: in CRecompiler::RecompilerMain_Lookup when TriggerAddressException has occured, update the PC before checking if valid
2025-02-13 12:22:52 +10:30
8ae9d7b9ff
Core: In R4300iOp::ExecuteOps only update UpdateInstructionMemory at the start of the loop
2025-02-13 12:19:22 +10:30
b8a514a483
core: Create instruction region to update after a block
2025-02-06 16:09:31 +10:30
4a68941c08
Core: Speed up some debugger usage in interepter if not being used
2025-02-06 12:24:39 +10:30
fd062a288a
Core: Convert interpter FPU ops to use softfloat
2025-02-04 07:15:24 +10:30
00a978ca1b
Core: add edge condition test to DDIV in interpter
2025-01-31 06:18:36 +10:30
c7d8a70a4d
Core: fix jump in CX86RecompilerOps::CompileSystemCheck
2024-12-27 09:02:37 +10:30
bfa3788562
Core: CX86RecompilerOps::COP1_D_Opcode fix return type of floating point register
2024-12-26 14:29:52 +10:30
3c7e71adca
Core: Fix up CX86RecompilerOps::COP1_D_Opcode for the registers it is using
2024-12-26 14:16:26 +10:30
fc79cb0344
Core: Add DwordLower for cvt.w
2024-12-26 09:35:07 +10:30
7e74b98d5b
Core: Fix up labels in CX86RecompilerOps::COP1_S_CVT
2024-12-19 21:59:42 +10:30
57f278416e
core: better handling of fpu registers with COP1_S_Opcode
2024-12-19 19:09:31 +10:30
13a974e687
Core: in CX86RecompilerOps::COP1_CT ignore write to other registers
2024-12-19 09:58:30 +10:30
fba1c4bc3b
Core: Fix up bug in CX86RecompilerOps::SPECIAL_AND
2024-12-19 09:57:25 +10:30
473aeba2cf
Core: Fix order of value in call to CMipsMemoryVM::SD_VAddr32 in recompiler
2024-12-12 21:22:32 +10:30
5d64b3d920
Core: Better handling of Storing non 32bit values to non memory
2024-12-12 16:50:36 +10:30
3164caf2d0
Core: allow Store/load ops be forced to 32bit version
2024-12-08 11:15:39 +10:30
8392ea5c0f
Core fix up load states
2024-12-06 21:50:31 +10:30
c6b41da926
Add Overclock modifier to Defaults panel
2024-12-05 17:30:59 +10:30
77cd679756
Core: Fix a bug in CX86RecompilerOps::SPECIAL_DIV
2024-12-05 17:05:52 +10:30
fc1210aac5
Core: Do not allow CX86RecompilerOps::SPECIAL_DSRL32 and CX86RecompilerOps::SPECIAL_DSRA32 to write to R0
2024-12-05 11:25:20 +10:30
1e4ab04121
Core: Fix up CX86RecompilerOps::SPECIAL_DSUB when rd == rt
2024-12-05 11:06:42 +10:30
04c1c3d024
Core: Fix up CX86RecompilerOps::SPECIAL_DADD
2024-12-05 10:03:45 +10:30
1f3ef6d505
Core: CX86RecompilerOps::SPECIAL_NOR Ignore write to r0
2024-11-28 15:54:36 +10:30
95015302d6
Core: Have CX86RecompilerOps::SPECIAL_XOR treat R0 as 64bit constant
2024-11-28 15:38:54 +10:30
a3c777ed84
Core: Have CX86RecompilerOps::SPECIAL_AND unmap the register on const write
2024-11-28 15:14:26 +10:30
0de0bea07a
Core: Ignore write in CX86RecompilerOps::SPECIAL_OR
2024-11-28 12:37:42 +10:30
8d69671e93
Core: CX86RecompilerOps::ADDIU should not ignore when not 32bit mapped
2024-11-28 12:29:35 +10:30
52d904702f
Core: With CONST64 CX86RegInfo::WriteBackRegisters might not write the high 32bit correct
2024-11-28 11:39:41 +10:30
d5367d9291
Core: Better handling of SW with address not sign extended
2024-11-28 11:02:38 +10:30
fd05d9f42f
core: if lwl or lwr, in CX86RecompilerOps::CompileLoadMemoryValue, make sure that we are loading rt
2024-11-21 21:33:42 +10:30
315d5b9e66
Core: When running as recompiler in 32bit mode, if LW/SW are in delay slots on block boundaries use 32bit interpter functions
2024-11-21 19:13:56 +10:30
5e1a40fffb
Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1
2024-11-21 11:10:01 +10:30
48b3e5a9a2
Core: Zip load in CN64System::LoadState uses utf16 path
2024-11-21 10:48:16 +10:30
Squall Leonhart