zilmar
|
23cff4d7c5
|
Core: Add x86 asm opcode Jnp
|
2024-01-04 12:31:26 +10:30 |
|
zilmar
|
91a8a828d7
|
Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW
|
2024-01-04 12:01:21 +10:30 |
|
zilmar
|
320769d991
|
Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr
|
2024-01-04 10:33:07 +10:30 |
|
zilmar
|
dafa1fb24d
|
Core: Have COP1_W_CVT_S handle the initialization of exceptions
|
2023-12-28 11:19:06 +10:30 |
|
zilmar
|
17288c90c0
|
Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32
|
2023-12-28 10:23:18 +10:30 |
|
zilmar
|
e2306e3541
|
Core: Get COP1_S_CVT_W to handle inexact
|
2023-12-28 09:21:53 +10:30 |
|
zilmar
|
8399fdb893
|
Core: Clear the Divide-by-zero flag
|
2023-12-21 21:24:33 +10:30 |
|
zilmar
|
d14a639a62
|
Core: Implement COP1_S_DIV with fpu exceptions
|
2023-12-21 14:11:29 +10:30 |
|
zilmar
|
8e54ec8c8e
|
Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis
|
2023-12-21 14:10:21 +10:30 |
|
zilmar
|
b263ee10b0
|
Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0
|
2023-12-21 10:41:16 +10:30 |
|
zilmar
|
1810bfda5c
|
Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops
|
2023-12-21 10:38:49 +10:30 |
|
zilmar
|
2c1610cfe2
|
Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode
|
2023-12-21 10:37:27 +10:30 |
|
zilmar
|
6610ae3058
|
Core: Have R4300iInstruction in CRecompilerOpsBase
|
2023-12-21 10:34:03 +10:30 |
|
zilmar
|
8e3fb3e302
|
Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference
|
2023-12-21 10:26:10 +10:30 |
|
zilmar
|
c8e73ba18e
|
Core: Handle unaligned SW exception in the recompiler
|
2023-12-14 23:04:26 +10:30 |
|
zilmar
|
972943cff7
|
Core: Allow LW to R0 be able to generate an exception
|
2023-12-14 17:21:52 +10:30 |
|
zilmar
|
89a6eaf9d1
|
Core: Add RecordLLAddress for 32bit register pointer
|
2023-12-14 13:52:15 +10:30 |
|
zilmar
|
67f5e4f854
|
Core: in LL for recompiler handle storing the address in COP[17]
|
2023-12-14 13:10:20 +10:30 |
|
zilmar
|
d5a5f4cdac
|
Core: Have Store Instruc rdb and user rdb matching
|
2023-12-14 12:21:03 +10:30 |
|
zilmar
|
5fec3f8d31
|
Core: remove the global of g_TLB
|
2023-12-14 12:09:24 +10:30 |
|
zilmar
|
c67f3f0e97
|
Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it
|
2023-12-14 11:18:07 +10:30 |
|
zilmar
|
15175d3fe2
|
Core: Fix bug in not creating save state correctly
|
2023-12-07 17:43:48 +10:30 |
|
zilmar
|
de1288bdca
|
Core: remove try/catch around Interpreter cpu
|
2023-11-30 21:15:14 +10:30 |
|
zilmar
|
df56964c96
|
Android: Remove unneeded log call
|
2023-11-30 21:13:27 +10:30 |
|
zilmar
|
5671f2b759
|
Android: Update how Addu cause android studio was not sign extending result
|
2023-11-30 21:12:53 +10:30 |
|
Derek "Turtle" Roe
|
acbb8f85a8
|
Fix typo in support window code (#2395)
* Fix typo in support window
* Fix the typo for real
|
2023-11-23 22:54:19 +10:30 |
|
zilmar
|
01673dac8d
|
Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
|
2023-11-23 14:20:48 +10:30 |
|
zilmar
|
d47b49d4b5
|
Core: Fix clang issue
|
2023-11-16 18:24:47 +10:30 |
|
zilmar
|
542afc4514
|
Core: remove some accidental added debug code
|
2023-11-16 18:16:35 +10:30 |
|
zilmar
|
ee714e2462
|
Core: On unmap base addresses reset to the correct address
|
2023-11-16 18:14:15 +10:30 |
|
zilmar
|
8f4f434820
|
Core: Get Fast tlb to just be 32bit
|
2023-11-16 17:11:05 +10:30 |
|
zilmar
|
dcb6969067
|
Core: Have entryHI use functions to set/get parts
|
2023-11-16 09:19:24 +10:30 |
|
zilmar
|
a0130ff896
|
Core: Convert %I64U to %llx
|
2023-11-16 09:03:32 +10:30 |
|
zilmar
|
e46ffde6b3
|
fix clang formatting
|
2023-11-09 12:59:40 +10:30 |
|
zilmar
|
296b7cf1cf
|
Android: Force RSP to be interpret
|
2023-11-09 12:45:36 +10:30 |
|
zilmar
|
0c8b10bbc7
|
Android: Get RSP core to compile on android
|
2023-11-09 11:53:06 +10:30 |
|
zilmar
|
09cc3442a2
|
Android: fix compile bug
|
2023-11-02 20:27:38 +10:30 |
|
zilmar
|
6fbc5c0264
|
Android: Move hle audio code in to main rsp plugin
|
2023-11-02 20:06:58 +10:30 |
|
zilmar
|
e6edbc6c82
|
Fix clang formatting
|
2023-10-27 10:14:21 +10:30 |
|
zilmar
|
4770d29ec0
|
Core: Get system events to be internal not global
|
2023-10-26 19:59:11 +10:30 |
|
zilmar
|
d3f4132770
|
Android: When listing a rom not in rdb, use game file instead
|
2023-10-26 11:18:24 +10:30 |
|
zilmar
|
b74e21d056
|
Android: Show base dir to splash logs when starting
|
2023-10-26 11:17:49 +10:30 |
|
zilmar
|
bf480623bd
|
[Android] Add Android/Bridge to clang checking
|
2023-10-26 11:05:20 +10:30 |
|
zilmar
|
8f062975c3
|
Core: improve DisplayControlRegHandler::Write32
|
2023-10-19 19:28:38 +10:30 |
|
zilmar
|
d6a2ae80c1
|
Core: Remove SystemRegisters
|
2023-10-19 14:56:53 +10:30 |
|
zilmar
|
d58168bcb9
|
Core: R4300iOp access the registers directly, not through CSystemRegisters
|
2023-10-19 12:52:33 +10:30 |
|
zilmar
|
4d78f56aa2
|
Core: In R4300iOp have a member variable for system, reg, mmu
|
2023-10-19 12:31:26 +10:30 |
|
zilmar
|
ae0097550f
|
Core: Make R4300iOp opcodes not static
|
2023-10-19 11:43:32 +10:30 |
|
zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
d3edbf6dda
|
Core: move CInterpreterCPU into R4300iOp
|
2023-10-19 09:32:42 +10:30 |