zilmar
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1edb5debdf
|
Core: have CRecompiler::RecompilerMain_VirtualTable handle PC as 32bit and clean up recompiler memory reset
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2025-02-27 20:47:37 +10:30 |
|
zilmar
|
daa8dbc833
|
core: reset m_InstructionRegion on R4300iOp::ExecuteOps
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2025-02-21 12:00:41 +10:30 |
|
zilmar
|
8ae9d7b9ff
|
Core: In R4300iOp::ExecuteOps only update UpdateInstructionMemory at the start of the loop
|
2025-02-13 12:19:22 +10:30 |
|
zilmar
|
b8a514a483
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core: Create instruction region to update after a block
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2025-02-06 16:09:31 +10:30 |
|
zilmar
|
4a68941c08
|
Core: Speed up some debugger usage in interepter if not being used
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2025-02-06 12:24:39 +10:30 |
|
zilmar
|
fd062a288a
|
Core: Convert interpter FPU ops to use softfloat
|
2025-02-04 07:15:24 +10:30 |
|
zilmar
|
00a978ca1b
|
Core: add edge condition test to DDIV in interpter
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2025-01-31 06:18:36 +10:30 |
|
zilmar
|
3164caf2d0
|
Core: allow Store/load ops be forced to 32bit version
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2024-12-08 11:15:39 +10:30 |
|
zilmar
|
315d5b9e66
|
Core: When running as recompiler in 32bit mode, if LW/SW are in delay slots on block boundaries use 32bit interpter functions
|
2024-11-21 19:13:56 +10:30 |
|
zilmar
|
5750d3df80
|
Core: Have only one function to do what R4300iOp::ExecuteOps and R4300iOp::ExecuteCPU was doing
|
2024-10-24 09:59:41 +10:30 |
|
zilmar
|
08e1b3b39b
|
fix up clang formatting
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2024-09-26 18:54:54 +09:30 |
|
zilmar
|
62bf10e505
|
Core: Have fpu ops check the input of fs and ft at the same time
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2024-09-26 16:38:25 +09:30 |
|
zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
|
2024-06-06 14:09:12 +09:30 |
|
zilmar
|
0ff0d5234c
|
Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify
|
2024-05-23 11:43:19 +09:30 |
|
zilmar
|
703a09d034
|
Core: Remove protecting memory option
|
2024-05-09 17:56:28 +09:30 |
|
zilmar
|
f0f44c67f4
|
Core: Make mov.s the same as mov.d
|
2024-01-25 15:32:56 +10:30 |
|
zilmar
|
2231e8d6c0
|
Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64
|
2024-01-18 16:53:14 +10:30 |
|
zilmar
|
5fec3f8d31
|
Core: remove the global of g_TLB
|
2023-12-14 12:09:24 +10:30 |
|
zilmar
|
de1288bdca
|
Core: remove try/catch around Interpreter cpu
|
2023-11-30 21:15:14 +10:30 |
|
zilmar
|
5671f2b759
|
Android: Update how Addu cause android studio was not sign extending result
|
2023-11-30 21:12:53 +10:30 |
|
zilmar
|
8f4f434820
|
Core: Get Fast tlb to just be 32bit
|
2023-11-16 17:11:05 +10:30 |
|
zilmar
|
4770d29ec0
|
Core: Get system events to be internal not global
|
2023-10-26 19:59:11 +10:30 |
|
zilmar
|
d58168bcb9
|
Core: R4300iOp access the registers directly, not through CSystemRegisters
|
2023-10-19 12:52:33 +10:30 |
|
zilmar
|
4d78f56aa2
|
Core: In R4300iOp have a member variable for system, reg, mmu
|
2023-10-19 12:31:26 +10:30 |
|
zilmar
|
ae0097550f
|
Core: Make R4300iOp opcodes not static
|
2023-10-19 11:43:32 +10:30 |
|
zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
d3edbf6dda
|
Core: move CInterpreterCPU into R4300iOp
|
2023-10-19 09:32:42 +10:30 |
|
zilmar
|
d4dbc5a3f4
|
Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
|
2023-10-14 11:53:35 +10:30 |
|
zilmar
|
00c5057b17
|
Core: Make sure precision is correct for COP1_D_SQRT
|
2023-10-13 00:16:14 +10:30 |
|
zilmar
|
3a68d3d92a
|
Core: LL/LLD store address
|
2023-10-12 19:55:29 +10:30 |
|
zilmar
|
4e71221147
|
Core: Fix up FPU mode register location
|
2023-10-12 14:53:44 +10:30 |
|
zilmar
|
35105e814e
|
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
|
2023-10-05 09:54:41 +10:30 |
|
zilmar
|
e0c125e837
|
Core: Fix clang issue
|
2023-09-14 16:33:20 +09:30 |
|
zilmar
|
c02858c7a0
|
Core: Add LLD opcode
|
2023-09-14 16:31:37 +09:30 |
|
zilmar
|
ae4af8746b
|
Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
|
2023-09-14 13:09:11 +09:30 |
|
zilmar
|
a5a4873e84
|
Core: Have CRegisters::DoAddressError to not directly modify program counter
|
2023-09-14 11:37:21 +09:30 |
|
zilmar
|
2d09178449
|
Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions
|
2023-09-14 11:15:42 +09:30 |
|
zilmar
|
5da5dab3c5
|
Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
|
2023-09-14 11:09:28 +09:30 |
|
zilmar
|
fcd7257adc
|
Core: Change COP0 Status register to a struct breaking up the bits
|
2023-09-14 10:23:36 +09:30 |
|
zilmar
|
7199096748
|
Core: Merge CheckFPUException into CheckFPUResult64
|
2023-08-31 18:52:34 +09:30 |
|
zilmar
|
6884c8d2c9
|
Core: fix up how recompiler handles rounding
|
2023-08-17 15:24:57 +09:30 |
|
zilmar
|
b5db44c12d
|
Core: Get CheckFPUInput64Conv to return true on exception
|
2023-08-03 17:25:03 +09:30 |
|
zilmar
|
5ff45c43c4
|
Core: Get R4300iOp::CheckFPUInput64 to return true on exception
|
2023-08-03 17:11:56 +09:30 |
|
zilmar
|
bc1b027c94
|
Core: get CheckFPUInput32Conv to return true on exception
|
2023-08-03 16:24:54 +09:30 |
|
zilmar
|
930e463bbc
|
Core: Move TriggerException(EXC_FPE) into R4300iOp::CheckFPUInput32
|
2023-08-03 15:38:07 +09:30 |
|
zilmar
|
187bd64915
|
Core: Update how exceptions are handled with the recompiler
|
2023-06-08 16:25:05 +09:30 |
|
zilmar
|
a39ebe7d37
|
Core: Create InitFpuOperation
|
2023-05-27 10:01:19 +09:30 |
|
zilmar
|
b438fddf2e
|
Core: Add CP2 handling
|
2023-05-18 18:04:41 +09:30 |
|
zilmar
|
3b8dfce64a
|
Core: Convert DoBreakException to TriggerException
|
2023-05-18 11:47:00 +09:30 |
|
zilmar
|
b2c2a03a2e
|
Core: convert DoFloatingPointException to TriggerException
|
2023-05-18 11:41:20 +09:30 |