2012-12-19 09:30:18 +00:00
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#pragma once
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2022-01-04 05:41:52 +00:00
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#include <Project64-core\N64System\Mips\MemoryVirtualMem.h>
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2015-12-06 09:59:58 +00:00
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#include "TranslateVaddr.h"
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2022-01-04 05:41:52 +00:00
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#include <Project64-core\N64System\Recompiler\RecompilerOps.h>
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#include <Project64-core\N64System\Interpreter\InterpreterOps.h>
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#include <Project64-core\N64System\Mips\PifRam.h>
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#include <Project64-core\N64System\Mips\FlashRam.h>
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#include <Project64-core\N64System\Mips\Sram.h>
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#include <Project64-core\N64System\Mips\Dma.h>
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2022-01-04 21:44:03 +00:00
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#include <Project64-core\N64System\MemoryHandler\PeripheralInterfaceHandler.h>
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2022-01-04 05:41:52 +00:00
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#include <Project64-core\N64System\MemoryHandler\RDRAMInterfaceHandler.h>
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2022-01-03 23:37:52 +00:00
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#include <Project64-core\Settings\GameSettings.h>
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2012-12-19 09:30:18 +00:00
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2016-06-04 23:42:49 +00:00
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#ifdef __arm__
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#include <sys/ucontext.h>
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#endif
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2016-06-05 17:06:27 +00:00
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#ifndef _WIN32
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#include <signal.h>
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2021-05-18 11:51:36 +00:00
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// siginfo_t
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2016-06-05 17:06:27 +00:00
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#endif
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2015-09-30 17:45:30 +00:00
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/*
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2021-05-18 11:51:36 +00:00
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* TODO: Have address translation functions here?
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2016-07-04 09:25:39 +00:00
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* `return` either the translated address or the mask to XOR by?
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2015-11-08 18:04:32 +00:00
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*
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2021-05-18 11:51:36 +00:00
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* This will help us gradually be able to port Project64 to big-endian CPUs.
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2016-07-04 09:25:39 +00:00
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* Currently it is written to assume 32-bit little-endian, like so:
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*
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* 0xAABBCCDD EEFFGGHH --> 0xDDCCBBAA HHGGFFEE
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* GPR bits[63..0] b1b2b3b4 b5b6b7b8
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2015-11-08 18:04:32 +00:00
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*/
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2015-09-30 17:45:30 +00:00
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2016-07-06 20:14:12 +00:00
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#if defined(__i386__) || defined(_M_IX86)
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2016-07-04 07:51:11 +00:00
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class CX86RecompilerOps;
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2016-11-21 07:06:14 +00:00
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#elif defined(__arm__) || defined(_M_ARM)
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class CArmRecompilerOps;
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2016-07-06 20:14:12 +00:00
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#endif
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2015-09-07 16:16:36 +00:00
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2010-05-31 00:21:08 +00:00
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class CMipsMemoryVM :
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2015-11-08 18:04:32 +00:00
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public CTransVaddr,
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private R4300iOp,
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private CPifRam,
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private CFlashram,
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private CSram,
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2022-01-04 21:44:03 +00:00
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public CDMA,
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2022-01-03 23:37:52 +00:00
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private CGameSettings
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2010-05-31 00:21:08 +00:00
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{
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public:
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2022-01-04 05:41:52 +00:00
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CMipsMemoryVM(CRegisters & Reg, bool SavesReadOnly);
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2015-11-08 18:04:32 +00:00
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~CMipsMemoryVM();
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static void ReserveMemory();
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static void FreeReservedMemory();
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2022-01-03 23:56:14 +00:00
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bool Initialize(bool SyncSystem);
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void Reset(bool EraseMemory);
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2015-12-13 07:26:31 +00:00
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uint8_t * Rdram();
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2022-01-03 23:56:14 +00:00
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uint32_t RdramSize();
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2015-12-13 07:26:31 +00:00
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uint8_t * Dmem();
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uint8_t * Imem();
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uint8_t * PifRam();
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2018-12-09 04:26:11 +00:00
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CSram * GetSram();
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CFlashram * GetFlashram();
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2022-01-03 23:56:14 +00:00
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bool LB_VAddr(uint32_t VAddr, uint8_t & Value);
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bool LH_VAddr(uint32_t VAddr, uint16_t & Value);
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bool LW_VAddr(uint32_t VAddr, uint32_t & Value);
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bool LD_VAddr(uint32_t VAddr, uint64_t & Value);
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2015-12-13 07:26:31 +00:00
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2022-01-03 23:56:14 +00:00
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bool LB_PAddr(uint32_t PAddr, uint8_t & Value);
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bool LH_PAddr(uint32_t PAddr, uint16_t & Value);
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bool LW_PAddr(uint32_t PAddr, uint32_t & Value);
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bool LD_PAddr(uint32_t PAddr, uint64_t & Value);
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2015-12-13 07:26:31 +00:00
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2022-01-03 23:56:14 +00:00
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bool SB_VAddr(uint32_t VAddr, uint8_t Value);
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bool SH_VAddr(uint32_t VAddr, uint16_t Value);
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bool SW_VAddr(uint32_t VAddr, uint32_t Value);
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bool SD_VAddr(uint32_t VAddr, uint64_t Value);
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2015-12-13 07:26:31 +00:00
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2022-01-03 23:56:14 +00:00
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bool SB_PAddr(uint32_t PAddr, uint8_t Value);
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bool SH_PAddr(uint32_t PAddr, uint16_t Value);
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bool SW_PAddr(uint32_t PAddr, uint32_t Value);
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bool SD_PAddr(uint32_t PAddr, uint64_t Value);
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2015-11-08 18:04:32 +00:00
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int32_t MemoryFilter(uint32_t dwExptCode, void * lpExceptionPointer);
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2022-01-03 23:56:14 +00:00
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void UpdateFieldSerration(uint32_t interlaced);
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2016-06-04 23:42:49 +00:00
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#ifndef _WIN32
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2016-06-05 17:06:27 +00:00
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static bool SetupSegvHandler(void);
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2016-06-04 23:42:49 +00:00
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static void segv_handler(int signal, siginfo_t *siginfo, void *sigcontext);
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#endif
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2015-11-08 18:04:32 +00:00
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2021-05-18 11:51:36 +00:00
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// Protect the memory from being written to
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2022-01-03 23:56:14 +00:00
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void ProtectMemory(uint32_t StartVaddr, uint32_t EndVaddr);
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void UnProtectMemory(uint32_t StartVaddr, uint32_t EndVaddr);
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2015-11-08 18:04:32 +00:00
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2021-05-18 11:51:36 +00:00
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// Functions for TLB notification
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2015-11-08 18:04:32 +00:00
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void TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly);
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void TLB_Unmaped(uint32_t Vaddr, uint32_t Len);
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// CTransVaddr interface
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bool TranslateVaddr(uint32_t VAddr, uint32_t &PAddr) const;
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bool ValidVaddr(uint32_t VAddr) const;
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bool VAddrToRealAddr(uint32_t VAddr, void * &RealAddress) const;
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// Labels
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const char * LabelName(uint32_t Address) const;
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2010-05-31 00:21:08 +00:00
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private:
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2021-04-13 00:07:11 +00:00
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CMipsMemoryVM();
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CMipsMemoryVM(const CMipsMemoryVM&);
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CMipsMemoryVM& operator=(const CMipsMemoryVM&);
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2012-12-18 10:43:29 +00:00
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2016-07-06 20:14:12 +00:00
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#if defined(__i386__) || defined(_M_IX86)
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2016-11-27 20:28:13 +00:00
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friend class CX86RecompilerOps;
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2016-09-23 22:40:58 +00:00
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#elif defined(__arm__) || defined(_M_ARM)
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2016-11-27 20:28:13 +00:00
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friend class CArmRegInfo;
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friend class CArmRecompilerOps;
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2016-07-06 20:14:12 +00:00
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#endif
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2013-01-11 21:57:51 +00:00
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2015-12-13 07:26:31 +00:00
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static void RdramChanged(CMipsMemoryVM * _this);
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static void ChangeSpStatus();
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2015-11-08 18:04:32 +00:00
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static void ChangeMiIntrMask();
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2010-06-12 02:02:06 +00:00
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2015-12-13 07:26:31 +00:00
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bool LB_NonMemory(uint32_t PAddr, uint32_t * Value, bool SignExtend);
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bool LH_NonMemory(uint32_t PAddr, uint32_t * Value, bool SignExtend);
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bool LW_NonMemory(uint32_t PAddr, uint32_t * Value);
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2010-05-31 00:21:08 +00:00
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2015-12-13 07:26:31 +00:00
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bool SB_NonMemory(uint32_t PAddr, uint8_t Value);
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bool SH_NonMemory(uint32_t PAddr, uint16_t Value);
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bool SW_NonMemory(uint32_t PAddr, uint32_t Value);
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2010-05-31 00:21:08 +00:00
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2015-12-21 09:45:08 +00:00
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static void Load32RDRAMRegisters(void);
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2015-12-21 09:49:13 +00:00
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static void Load32SPRegisters(void);
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2015-12-21 09:52:59 +00:00
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static void Load32DPCommand(void);
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2015-12-21 09:56:24 +00:00
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static void Load32MIPSInterface(void);
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2015-12-21 10:01:56 +00:00
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static void Load32VideoInterface(void);
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2015-12-21 10:06:51 +00:00
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static void Load32AudioInterface(void);
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2015-12-21 19:59:17 +00:00
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static void Load32SerialInterface(void);
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2016-01-17 06:38:29 +00:00
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static void Load32CartridgeDomain1Address1(void);
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static void Load32CartridgeDomain1Address3(void);
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2015-12-21 21:03:14 +00:00
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static void Load32CartridgeDomain2Address1(void);
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static void Load32CartridgeDomain2Address2(void);
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2015-12-21 21:15:26 +00:00
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static void Load32PifRam(void);
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2015-12-21 21:24:37 +00:00
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static void Load32Rom(void);
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2015-12-21 09:45:08 +00:00
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2015-12-21 21:35:06 +00:00
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static void Write32RDRAMRegisters(void);
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2015-12-21 21:41:49 +00:00
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static void Write32SPRegisters(void);
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2015-12-21 21:49:58 +00:00
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static void Write32DPCommandRegisters(void);
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2015-12-22 05:31:13 +00:00
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static void Write32MIPSInterface(void);
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2015-12-22 05:40:19 +00:00
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static void Write32VideoInterface(void);
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2015-12-22 05:46:08 +00:00
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static void Write32AudioInterface(void);
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2015-12-22 06:02:08 +00:00
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static void Write32SerialInterface(void);
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2016-01-19 18:53:18 +00:00
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static void Write32CartridgeDomain2Address1(void);
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2015-12-22 06:09:27 +00:00
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static void Write32CartridgeDomain2Address2(void);
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2015-12-22 08:04:55 +00:00
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static void Write32PifRam(void);
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2015-12-21 21:35:06 +00:00
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2016-06-04 23:42:49 +00:00
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#if defined(__i386__) || defined(_M_IX86)
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2016-07-03 10:17:45 +00:00
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typedef struct _X86_CONTEXT
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2016-06-04 23:42:49 +00:00
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{
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uint32_t * Edi;
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uint32_t * Esi;
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uint32_t * Ebx;
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uint32_t * Edx;
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uint32_t * Ecx;
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uint32_t * Eax;
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uint32_t * Eip;
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uint32_t * Esp;
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uint32_t * Ebp;
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} X86_CONTEXT;
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static bool FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & context);
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#endif
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#ifdef __arm__
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2019-08-21 09:27:50 +00:00
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static void DumpArmExceptionInfo(uint32_t MemAddress, mcontext_t & context);
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2016-06-04 23:42:49 +00:00
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static bool FilterArmException(uint32_t MemAddress, mcontext_t & context);
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#endif
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2015-11-08 18:04:32 +00:00
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void UpdateHalfLine();
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void FreeMemory();
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2012-12-18 10:43:29 +00:00
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2022-01-03 23:56:14 +00:00
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static uint8_t * m_Reserve1, *m_Reserve2;
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2022-01-04 05:41:52 +00:00
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CRegisters & m_Reg;
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2022-01-04 21:44:03 +00:00
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PeripheralInterfaceHandler m_PeripheralInterfaceHandler;
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2022-01-04 05:41:52 +00:00
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RDRAMInterfaceHandler m_RDRAMInterfaceHandler;
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2022-01-03 23:56:14 +00:00
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uint8_t * m_RDRAM, *m_DMEM, *m_IMEM;
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uint32_t m_AllocatedRdramSize;
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bool m_RomMapped;
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uint8_t * m_Rom;
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uint32_t m_RomSize;
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bool m_RomWrittenTo;
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uint32_t m_RomWroteValue;
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bool m_DDRomMapped;
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uint8_t * m_DDRom;
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uint32_t m_DDRomSize;
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uint32_t m_HalfLine;
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uint32_t m_HalfLineCheck;
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uint32_t m_FieldSerration;
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2010-05-31 00:21:08 +00:00
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2022-01-03 23:56:14 +00:00
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mutable char m_strLabelName[100];
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2015-11-08 18:04:32 +00:00
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size_t * m_TLB_ReadMap;
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size_t * m_TLB_WriteMap;
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2015-12-21 09:45:08 +00:00
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static uint32_t m_MemLookupAddress;
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static MIPS_DWORD m_MemLookupValue;
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static bool m_MemLookupValid;
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2016-06-29 13:40:36 +00:00
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static uint32_t RegModValue;
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2010-05-31 00:21:08 +00:00
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};
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